Apparatus and method for trace stream identification of multiple target processor events

• US 20040133823A1
• Filed: 12/05/2003
• Published: 07/08/2004
• Est. Priority Date: 12/17/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L., Thome, Bryan
• Granted Patent: US 7,325,169 B2
• Time in Patent Office: Days
• US Class Current: 714/39
• CPC Class Codes: G06F 11/3632 of specific synchronisation aspects
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program

Abstract

When a plurality of simultaneous, preselected target processor events are detected, a multiple-event sync marker is generated that identifies the preselected events and relates the occurrence of these events to timing trace stream. The sync marker for the plurality of preselected events differs from a single event sync marker by including at least one additional packet. The additional packet includes logic signals stored at locations related to each identified event.

Claims

1. For the testing of the operation of processing unit, a system for identifying the occurrence of a plurality of events in a processor unit, the system comprising:

timing trace apparatus responsive to signals from the processor unit, the timing trace apparatus generating a timing trace stream;

program counter trace apparatus responsive to signals from the processing unit, the program counter trace apparatus generating a program counter trace stream; and

synchronization apparatus applying periodic signals to the timing trace apparatus and to the program counter trace apparatus, the periodic signals;

wherein the program counter trace apparatus is responsive to plurality of simultaneous event signals, the program counter trace apparatus generating multiple-event sync marker signal group identifying the occurrence of the plurality of simultaneous events and relating the event signals to the timing trace stream and the program execution.

2. The system as recited in claim 1 wherein the marker signal group includes a program counter address, a timing index and a periodic sync ID.

3. The system as recited in claim 1 further comprising:

data trace apparatus responsive to signals from the processing unit, the data trace apparatus generating a data trace stream, wherein the periodic sync ID signals are applied to the data trace apparatus provide periodic sync markers in the data trace stream; and

a host processing unit, the host processing unit responsive to the timing trace stream, the program counter trace stream and the data trace stream, the host processing unit reconstructing the processing activity of the processing unit from the trace streams.

4. The method for communicating an occurrence of a reset signal from a target processor unit to a host processing unit, the method comprising:

generating a timing trace stream, a program counter trace stream, and data trace stream, and

in the program counter trace stream, including a marker signal group indicating a simultaneous occurrence of a plurality of event signals and relating the occurrence to the data trace stream, to the timing trace stream, and to the program execution.

5. The method as recited in claim 4 further including:

in the marker signal group, including a periodic sync ID, a timing index and a program counter address.

6. In a processing unit test environment wherein a target processor transmits a plurality of trace streams to a host processing unit, a marker signal group included in a trace signal stream, the marker signal group comprising:

indicia of the simultaneous occurrence of a plurality of event signals;

indicia of the relationship of the occurrence of the reset signal to the target processor clock; and

indicia of the relationship of the occurrence of the event signals to the target processor program execution.

7. In a target processing unit generating trace test signals for transfer to a host processing unit, program counter trace generation apparatus comprising:

a storage unit;

a decoder unit responsive to a rest signal for storing a signal group identifying a first event signal in the storage unit in a first location in the storage unit, the decoder unit generating a control signal, the decoder unit generating a second control signal when multiple simultaneous events are identified;

a gate unit responsive to the control signal, the gate unit transmitting processor signals applied thereto to the storage unit for storage at defined locations, the signals stored in the storage unit forming a portion of a multiple-event sync marker;

a multiple-event gate unit responsive to the second control signal for storing indicia of additional event signals in the storage unit; and

a FIFO unit coupled to the storage unit, the FIFO unit receiving the multiple-event sync marker when the multiple-event sync marker has been assembled, the FIFO unit transferring the multiple-event sync marker to the host processing unit.

8. The program counter trace apparatus as recited in claim 7 wherein the signals applied to the gate unit include a program counter address, a periodic sync ID, and a timing index.

9. The program counter trace apparatus as recited in claim 8 wherein the multiple-event sync marker signal includes a plurality of packets.

10. The program counter trace apparatus as recited in claim 7 wherein the sync markers in the FIFO unit are transferred from the unit in response to third control signals.