Electrostatic Discharge Protection Networks For Triple Well Semiconductor Devices

• US 20040135141A1
• Filed: 01/09/2003
• Published: 07/15/2004
• Est. Priority Date: 01/09/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pequignot, James P, Voldman, Steven H., Stout, Douglas W., Sloan, Jeffrey H.
• Granted Patent: US 6,891,207 B2
• Time in Patent Office: Days
• US Class Current: 257/46
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration. A control network can be used to control the biasing when the semiconductor devices are used in a series configuration.

Claims

1. A semiconductor device comprising:

a substrate of a first dopant type;

a first doped region residing within the substrate, the doped region being of a second dopant type;

a second doped region residing above the first doped region;

a third doped region residing above the second doped region;

an edge structure defining the edges of the third doped region; and

a fourth structure separating the second doped region from the substrate.

2. The semiconductor device of claim 1 wherein the fourth structure is a doped region of the second dopant type.

3. The semiconductor device of claim 1 wherein the fourth structure is an insulator.

4. The semiconductor device of claim 3 wherein the fourth structure has an insulated sidewall.

5. The semiconductor device of claim 1 wherein the edge structure is a shallow trench isolation.

6. The semiconductor device of claim 1 wherein the edge structure is a poly silicon gate structure.

7. The semiconductor device of claim 3 wherein the fourth structure is a Trench Isolation (TI).

8. The semiconductor device of claim 3 wherein the fourth structure is a Deep Trench Isolation (DTI).

9. A semiconductor comprising:

a plurality of devices each one of the devices having;

a substrate of a first dopant type;

a first doped region residing within the substrate, the doped region being of a second dopant type;

a second doped region residing above the first doped region;

a third doped region residing above the second doped region;

an edge structure defining the edges of the third doped region and

a fourth structure separating the second doped region from the substrate.

10. The semiconductor of claim 9 wherein a first one of the plurality of devices is coupled serially to a second one of the plurality of devices.

11. The semiconductor of claim 10 wherein the edge structure of the second one of the plurality of devices is coupled to a reference control network

12. The semiconductor of claim 11 wherein the reference control network controls the biasing of the edge structure.

13. The semiconductor of claim 11 wherein the first doped region is connected to a reference control network for controlling the biasing of the first doped region.

14. The semiconductor of claim 12 wherein the fourth structure of each one of the devices is a doped region of the second dopant type.

15. The semiconductor of claim 12 wherein the fourth structure of each one of the devices is an insulator.

16. The semiconductor of claim 15 wherein the fourth structure of each one of the devices has an insulated side wall.

17. The semiconductor of claim 12 wherein one of the edge structures of one of the devices is a polysilicon gate.

18. The semiconductor of claim 12 wherein one of the fourth structures of one of the devices is a Trench Insolation (TI).

19. A circuit comprising:

a plurality of triple well diodes coupled in series with one another, each one of the diodes having a shared n doped region.

20. The circuit of claim 19 further comprising:

a control device coupled to the shared n doped region to control the biasing of the shared n doped region.