Semiconductor device with MOS transistors with an etch-stop layer having an improved residual stress level and method for fabricating such a semiconductor device

• US 20040135234A1
• Filed: 11/04/2003
• Published: 07/15/2004
• Est. Priority Date: 11/05/2002
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Morin, Pierre, Regolini, Jorge Luis
• Granted Patent: US 7,187,038 B2
• Time in Patent Office: Days
• US Class Current: 257/635
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a substrate, MOS transistors in the substrate, and a dielectric layer on the MOS transistors. Contact holes are formed through the dielectric layer to provide electrical connection to the MOS transistors. An etch-stop layer is between the MOS transistors and the dielectric layer. The etch-stop layer includes a first layer of material having a first residual stress level and covers some of the MOS transistors, and a second layer of material having a second residual stress level and covers all of the MOS transistors. The respective thickness of the first and second layers of material, and the first and second residual stress levels associated therewith are selected to obtain variations in operating parameters of the MOS transistors.

Claims

1. Semiconductor device with MOS transistors, comprising a semiconductor substrate (10) in which the transistors are formed, a dielectric layer (14) which covers the substrate and in which contact holes (16) are etched, and an etch-stop layer (18) interposed between the substrate and the dielectric layer, characterized in that the etch-stop layer includes a first layer (I) of material which has a first residual stress level and covers some of the transistors, and a second layer (II) of material which has a second residual stress level and covers all of the transistors, the thicknesses (e1, e2) of the first and second layers, and the first and second residual stress levels (σ

₁, σ

₂), being selected so as to obtain variations in operating parameters of the transistors with respect to transistors covered by the first layer of material.

2. Device according to claim 1, characterized in that the MOS transistors include NMOS-type transistors and PMOS-type transistors, and in that the first and second layers of material (I, II) have opposite residual stress levels.

3. Device according to claim 2, characterized in that the thicknesses (e1, e2) of the first layer and of the second layer, and the residual stress levels (σ

₁, σ

₂) of the first layer and of the second layer, are determined so as to obtain a positive stress level above the NMOS transistors and a negative stress level above the PMOS transistors.

4. Device according to one of claims 2 and 3, characterized in that the first layer has a negative stress level and covers the PMOS-type transistors, and the second layer has a positive stress level.

5. Device according to one of claims 2 and 3, characterized in that the first layer has a positive stress level and covers the NMOS-type transistors, and the second layer has a negative stress level.

6. Device according to any one of claims 1 to 5, characterized in that the zone of the second layer covering the first layer has a substantially zero residual stress.

7. Method for fabricating a semiconductor device with MOS transistors according to any one of claims 1 to 6, comprising formation of the transistors in a semiconductor substrate (10), deposition of an etch-stop layer (18) on the transistors, deposition of a dielectric layer on the etch-stop layer and etching of connection holes in the dielectric layer, characterized in that the step of depositing the etch-stop layer comprises the deposition of a first layer (I) of material which has a first residual stress level and covers some of the transistors, and the deposition on the first layer of a second layer (II) of material which has a second residual stress level and covers all of the transistors, the thicknesses of the first and second layers, and the first and second residual stress levels, being selected so as to obtain variations in operating parameters of the transistors with respect to transistors covered by the first layer of material.

8. Method according to claim 7, characterized in that the step of depositing the first layer involves deposition of the said layer on all of the transistors, deposition of masks at the positions of the transistors of the said some of the transistors, etching of the exposed layer and removal of the masks.

9. Method according to one of claims 7 and 8, characterized in that, subsequent to the step of depositing the second layer, a localized treatment of the material of the second layer (II) is carried out at the positions of the transistors of the said some of the transistors so as to locally modify the stress level of the second layer.

10. Method according to claim 9, characterized in that the treatment of the second layer is carried out by ion implantation.

11. Method according to claim 10, characterized in that the treatment of the second layer is carried out by ion implantation of Ge.