Substrate for mounting a semiconductor chip

• US 20040135266A1
• Filed: 03/01/2004
• Published: 07/15/2004
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Koh, Liang Kng Ian
• Granted Patent: US 7,294,853 B2
• Time in Patent Office: Days
• US Class Current: 257/782
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/78301 Capillary
• CPC Class Codes: H01L 2224/85181 connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
• CPC Class Codes: H01L 2224/859 involving monitoring, e.g. feedback loop
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/78 Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 24/85 using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A substrate (1) is formed from a non-electrically conducting material and is for mounting a semiconductor chip (10). The substrate has a semiconductor chip mounting portion (6). A number of first electrically conducting contact portions (5) are formed on the surface of the material and associated with the mounting portion (6). A second electrically conducting contact portion (3) is formed on the surface of the material, and the second electrically conducting contact portion (3) is adapted to be coupled to testing equipment. A number of electrically conducting paths (4) are formed on the surface of the material. The conducting paths (4) electrically connect the second electrically conducting contact portion (3) to a minority of the first electrically conducting contact portions (5).

Claims

1. A substrate comprising a non-electrically conducting material for mounting a semiconductor chip, the substrate comprising a semiconductor chip mounting portion, a number of first electrically conducting contact portions formed on the surface of the material and associated with the mounting portion, a second electrically conducting contact portion formed on the surface of the material, the second electrically conducting contact portion being adapted to be coupled to testing equipment, and a number of electrically conducting paths formed on the surface of the material, the conducting paths electrically connecting the second electrically conducting contact portion to a minority of the first electrically conducting contact portions.

2. A substrate according to claim 1, wherein less than 10% of the first is contact portions are connected to the second contact portion.

3. A substrate according to claim 1, wherein a maximum of ten of the first contact portions are connected to the second contact portion.

4. A substrate according to claim 3, wherein a maximum of five first contact portions are connected to the second contact portions.

5. A substrate according to claim 4, wherein there is only one electrically conducting path, the one electrically conducting path electrically connecting only one first contact portion to the second contact portion.

6. A substrate according to any of the preceding claims, wherein one of the first contact portions connected to the second contact portion is coupled to a ground contact on the substrate.

7. A substrate according to claim 6, wherein the ground contact is on the mounting portion.

8. A substrate according to any of the preceding claims, wherein the substrate is for mounting a wireless communication chip.

9. A substrate according any of the preceding claims, wherein the substrate comprises a number of mounting portions, each mounting portion having a number of first contact portions associated therewith.