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Fabrication method of semiconductor integrated circuit device and its testing apparatus

  • US 20040135593A1
  • Filed: 01/07/2004
  • Published: 07/15/2004
  • Est. Priority Date: 10/03/2000
  • Status: Abandoned Application
First Claim
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1. A semiconductor integrated circuit device fabrication method comprising:

  • performing an electrical test to a plurality of wafer surface regions over a major surface of a wafer, each of said plurality of wafer surface regions including a plurality of chip regions, using a plate holding structure integrally holding a plurality of wiring/stylus composite plates, each of said wiring/stylus composite plates including a first wiring film structure having a plurality of test stylus sections electrically connected thereto, each of the test stylus sections having a stylus tip portion contacting one of a plurality of terminals in one of the wafer surface regions in said performing the electrical test.

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