Fabrication method of semiconductor integrated circuit device and its testing apparatus

• US 20040135593A1
• Filed: 01/07/2004
• Published: 07/15/2004
• Est. Priority Date: 10/03/2000
• Status: Abandoned Application

• Current Assignee: Akio Hasebe, Akira Seito, Masaaki Namba, Naoto Ban, Ryuji Kohno, Yasuhiro Motoyama, Yuji Wada
• Original Assignee: Akio Hasebe, Akira Seito, Masaaki Namba, Naoto Ban, Ryuji Kohno, Yasuhiro Motoyama, Yuji Wada
• Inventors: Hasebe, Akio, Kohno, Ryuji, Wada, Yuji, Motoyama, Yasuhiro, Seito, Akira, Ban, Naoto, Namba, Masaaki
• Application Number:
  US10/751,937
• Publication Number:
  US 20040135593A1
• Time in Patent Office: Days
• US Class Current: 324/760
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00

Abstract

A testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these blocks and employs the wafer full surface simultaneous contact system of the divided contactor integration type. Each probe of the silicon contactor is equally placed in contact in the predetermined pressure with each test pad of each chip of the test wafer by mechanically pressuring each silicon contactor block which moves individually, the test control signal is supplied to each chip and this test result signal is obtained for the wafer level burn-in test.

Claims

1. A semiconductor integrated circuit device fabrication method comprising:

performing an electrical test to a plurality of wafer surface regions over a major surface of a wafer, each of said plurality of wafer surface regions including a plurality of chip regions, using a plate holding structure integrally holding a plurality of wiring/stylus composite plates, each of said wiring/stylus composite plates including a first wiring film structure having a plurality of test stylus sections electrically connected thereto, each of the test stylus sections having a stylus tip portion contacting one of a plurality of terminals in one of the wafer surface regions in said performing the electrical test.

2. A semiconductor integrated circuit device fabrication method according to claim 1, wherein said electrical test is a wafer level burn-in test.