Clock multiplier circuit

• US 20040135601A1
• Filed: 07/23/2003
• Published: 07/15/2004
• Est. Priority Date: 07/23/2002
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Aman, Norihisa
• Granted Patent: US 6,876,236 B2
• Time in Patent Office: Days
• US Class Current: 327/116
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

Providing a clock multiplier circuit which generates a multiple clock having a stable frequency from a reference clock without using analog devices

The above clock multiplier circuit comprises: a ring oscillator which oscillates at a sufficiently higher frequency than that of the multiple clock; a reference clock counter for counting the sampling output of the reference clock by the output clock of the ring oscillator to obtain the count value of the half cycle of the reference clock; and a multiple clock counter which, in case the value obtained by dividing the count value of the half cycle of the obtained reference clock by the multiplication factor externally given is defined as a multiple count value, inverts the output of the multiple clock output each time it counts the multiple count value by the output clock of the ring oscillator.

Claims

1. A clock multiplier circuit which outputs a multiple clock having a frequency of a multiplication factor externally given with regard to a reference clock, comprising:

a ring oscillator which oscillates at a sufficiently higher frequency than that of said multiple clock;

a reference clock counter for counting the sampling output of the reference clock by the output clock of the ring oscillator to obtain the count value of the half cycle of the reference clock; and

a multiple clock counter which, in case the value obtained by dividing the count value of the half cycle of said reference clock by said multiplication factor is defined as a multiple count value, inverts the output of said multiple clock output each time it counts said multiple count value by the output clock of said ring oscillator.

2. A clock multiplier circuit according to claim 1, wherein said ring oscillator comprises an odd number of inverter stages.

3. A clock multiplier circuit according to claim 1 or 2, wherein said multiple clock counter starts counting of a multiple count value in synchronization with the inversion per half cycle of said reference clock.

4. A clock multiplier circuit according any one of claims through 3, further comprising:

an unlock detection circuit;

wherein said multiple clock counter generates a count and pulse each time it counts said multiple count value and that said unlock detection circuit determines detection of an unlock in case said count end pulse is not detected within a cycle of said reference clock and restarts said ring oscillator based on determination of said detection of unlock.