Fast locking phase-locked loop

• US 20040135639A1
• Filed: 09/08/2003
• Published: 07/15/2004
• Est. Priority Date: 09/06/2002
• Status: Active Grant

• Current Assignee: True Circuits, Inc.
• Original Assignee: True Circuits, Inc.
• Inventors: Maneatis, John G.
• Granted Patent: US 7,078,977 B2
• Time in Patent Office: Days
• US Class Current: 331/16
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/1072 by changing characteristics of the charge pump, e.g. changing the gain
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A phase-locked loop system, including a voltage controlled oscillator coupled with an error detector in a feedback configuration, so as to produce an output signal having a desired characteristic that is based on a reference signal. The system also includes a charge pump system coupled with the voltage controlled oscillator and configured to produce currents to control phase and frequency of the output signal. The charge pump system includes at least two charge pumps, one being configured to effect more rapid changes in the output signal than the other. This charge pump may be configured to deliver a higher charge pump current than the other charge pump, and/or may be activated intermittently upon detection of cycle slippage or another condition detectable during operation of the phase-locked loop system.

Claims

1. A fast-locking phase-locked loop system configured to produce an output signal having a desired characteristic based on an applied reference signal, comprising:

a voltage controlled oscillator configured to produce the output signal;

a charge pump system operatively coupled with the voltage controlled oscillator and configured to generate currents that control the phase and frequency of the output signal produced by the voltage controlled oscillator, where the charge pump system includes;

at least one run-time charge pump configured to repeatedly pump charge during run-time operation of the phase-locked loop so as to produce ongoing phase adjustments of the output signal as needed to maintain the phase-locked loop in a locked condition; and

at least one additional charge pump configured to provide a charge pump current of substantially larger magnitude than that provided by the run-time charge pump so as to provide frequency adjustment of the output signal upon detection of cycle slippage between the output signal and the reference signal.

2. The system of claim 1, further comprising an error detector operatively coupled with the charge pump system and configured to provide an error signal to the charge pump system upon which the charge pump currents are based.

3. The system of claim 2, where the error detector includes a cycle slip detector configured to detect cycle slippage between the output signal and the reference signal.

4. The system of claim 3, where the error detector includes a phase frequency detector coupled upstream of the cycle slip detector, the phase frequency including a U output configured to activate when the output signal lags a desired frequency or phase which is based on the reference signal, the phase frequency detector also including a D output configured to activate when the output signal leads the desired frequency or phase.

5. The system of claim 3, where the cycle slip detector is configured to apply an activating signal to the additional charge pump upon detection of cycle slippage occurring between the output signal and the reference signal.

6. The system of claim 5, where the cycle slip detector includes edge-triggered latches coupled with the U and D outputs of the phase frequency detector.

7. The system of claim 6, where the latches are triggered by edges of input signals applied to the phase frequency detector.

8. The system of claim 1, further comprising:

a bias generator operatively coupled with the voltage controlled oscillator and configured to generate a biasing current and an associated biasing signal based on differences between the output signal and the desired characteristic, where the phase-locked loop system is configured so that;

the biasing current produces a regulated bias generator voltage within the bias generator;

the voltage controlled oscillator produces the output signal in response to a VCO current generated via application of the biasing signal from the bias generator;

the VCO current produces a regulated VCO voltage within the voltage controlled oscillator; and

the regulated bias generator voltage matches the regulated VCO voltage free of any direct coupling between the bias generator and the regulated VCO voltage.

9. The system of claim 8, where the bias generator is configured to dynamically generate the biasing signal free of any predetermined external bias.

10. The system of claim 8, where the voltage controlled oscillator includes a plurality of VCO stages.

11. The system of claim 10, where the VCO stages are coupled in parallel between a positive voltage supply and a regulated ground node.

12. The system of claim 11, where the VCO current is produced by a VCO current source that is biased by the biasing signal, and where the VCO current source is coupled in series between a negative voltage supply and the regulated ground node.

13. The system of claim 11, where the VCO stages are coupled in parallel between a negative voltage supply and a regulated supply node.

14. The system of claim 13, where the VCO current is produced by a VCO current source that is biased by the biasing signal, and where the VCO current source is coupled in series between a positive voltage supply and the regulated supply node.

15. The system of claim 1, where the charge pump system and voltage controlled oscillator are configured to be driven at least partially in response to application of a shared biasing signal which is generated based on detected differences between the output signal and the desired characteristic, and where the biasing signal is coupled into the charge pump system via an isolated input path configured to inhibit undesired signal coupling from the charge pump system to the voltage controlled oscillator via the shared biasing signal.

16. The system of claim 15, where the isolated input path includes a current mirror configured to produce a mirrored copy of the biasing signal for use within the charge pump system.

17. The system of claim 15, further comprising a bias generator configured to dynamically generate the biasing signal free of any predetermined external bias.

18. The system of claim 15, where the voltage controlled oscillator includes a current source and a plurality of VCO stages connected to the current source via a regulated voltage node, the voltage controlled oscillator being configured to produce the output signal based upon current supplied via the regulated voltage node to the plurality of VCO stages.

19. The system of claim 15, where the biasing signal is generated by a bias generator that matches an effective impedance of the voltage controlled oscillator so that current supplied to the voltage controlled oscillator is substantially independent of supply and substrate noise.

20. The system of claim 1, further comprising a bias generator configured to generate a biasing signal via operation of a feedback loop responsive to currents generated by the charge pump system, where the voltage controlled oscillator is configured to produce the output signal in response to application of the biasing signal,

where charge pump output is applied to the bias generator along a proportional control path and an integrating control path, the proportional control path including a current mirror isolation mechanism to prevent capacitance on the proportional control path from affecting dynamic response of the bias generator feedback loop.

21. The system of claim 1, where the charge pump system is configured so that the charge pump current delivered by the additional charge pump is at least an order of magnitude greater than that delivered by the run-time charge pump.

22. In a phase-locked loop system configured to produce an output signal that tracks a reference signal at an output frequency that is x/y times a reference frequency of the reference signal, a fast-locking correction mechanism comprising:

a cycle slip detector configured to detect cycle slippage between the reference signal and the output signal, such detection being based upon reference intervals of the reference signal and output intervals of the output signal, a given reference interval being defined by two successive triggering edges of the reference signal and a given output interval being defined by (x/y+1) successive triggering edges of the output signal, and where cycle slippage is detected upon satisfaction of either of the following two conditions;

(a) more than one triggering edge of the reference signal have occurred since commencement of a current one of the output intervals; and

(b) more than x/y triggering edges of the output signal have occurred since commencement of a current one of the reference intervals; and

a charge pump system operatively coupled with the cycle slip detector and configured to pump charge while either of the above two conditions are satisfied so as to produce a corrective frequency adjustment of the output signal to cause the output signal to lock onto and track the reference signal.

23. In a phase-locked loop system configured to produce an output signal having a desired characteristic based on a reference signal, a fast-locking correction mechanism comprising:

a cycle slip detector configured to detect cycle slippage occurring between first and second periodic input signals applied to a phase frequency detector of the phase-locked loop system, where cycle slippage is detected while a complete cycle of the first periodic input signal has occurred within a current cycle of the second periodic input signal; and

a charge pump system operatively coupled with the cycle slip detector and configured to pump charge while cycle slippage is -detected so as to produce a corrective frequency adjustment of the output signal to cause the output signal to lock onto and track the reference signal.

24. The mechanism of claim 23, where the charge pump system includes at least one run-time charge pump configured to generate charge pump currents so as to produce phase corrections during normal run-time operation to maintain the phase-locked loop system in a locked or nearly locked state.

25. The mechanism of claim 24, where the charge pump system includes an additional charge pump configured to be activated only upon detection of cycle slippage between the first and second periodic input signals.

26. The mechanism of claim 25, where the additional charge pump is configured to produce charge pump currents that are at least an order of magnitude greater than charge pump currents produced by the run-time charge pump.

27. The mechanism of claim 25, where the phase-locked loop system is configured so that the additional charge pump is activated less often than the run-time charge pump.

28. The mechanism of claim 25, where the phase-locked loop system is configured so that the additional charge pump is activated only during startup of the phase-locked loop system or recovery of the phase-locked loop system from a dormant state.

29. A method of modifying an output signal in a phase locked loop system that is configured to cause the output signal to have a desired characteristic which is based on a reference signal, the method comprising:

continuously detecting whether cycle slippage has occurred between a first and a second periodic input signal that are applied to a phase frequency detector, where such cycle slippage is defined as occurring whenever a complete cycle of the first periodic input cycle occurs within a current cycle of the second periodic signal;

pumping charge to increase the frequency of the output signal while cycle slippage has occurred between the first and second periodic input signals.

30. A phase-locked loop system, comprising:

a voltage controlled oscillator coupled with an error detector in a feedback configuration so as to produce an output signal having a desired characteristic that is based on a reference signal; and

a charge pump system coupled with the voltage controlled oscillator and configured to produce currents to control phase and frequency of the output signal,

where the charge pump system includes at least two charge pumps, one such charge pump being configured to deliver a higher charge pump current than the other to produce more rapid changes in the output signal than the other charge pump.

31. The system of claim 30, where the phase-locked loop system is configured to intermittently activate the higher-current charge pump upon satisfaction of a predetermined condition, where such predetermined condition is selected so as to be determinable during operation of the phase-locked loop.

32. The system of claim 31, where the phase-locked loop system is configured to activate the higher-current charge pump only while cycle slippage has occurred between first and second period input signals that are applied to a phase frequency detector of the phase-locked loop system.

33. The system of claim 32, further comprising an error detector operatively coupled with the charge pump system and configured to provide an error signal to the charge pump system based on differences between the output signal and the desired characteristic, where the error detector includes a cycle slip detector operatively coupled with the higher-current charge pump via an enable line.

34. The system of claim 31, further comprising:

a bias generator operatively coupled with the voltage controlled oscillator and configured to generate a biasing current and an associated biasing signal based on differences between the output signal and the desired characteristic, where the phase-locked loop system is configured so that;

the biasing current produces a regulated bias generator voltage within the bias generator;

the voltage controlled oscillator produces the output signal in response to a VCO current generated via application of the biasing signal from the bias generator;

the VCO current produces a regulated VCO voltage within the voltage controlled oscillator; and

the regulated bias generator voltage matches the regulated VCO voltage free of any direct coupling between the bias generator and the regulated VCO voltage.

35. The system of claim 34, where the bias generator is configured to dynamically generate the biasing signal free of any predetermined external bias.

36. The system of claim 34, where the voltage controlled oscillator includes a plurality of VCO stages.

37. The system of claim 36, where the VCO stages are coupled in parallel between a positive voltage supply and a regulated ground node.

38. The system of claim 37, where the VCO current is produced by a VCO current source that is biased by the biasing signal, and where the VCO current source is coupled in series between a negative voltage supply and the regulated ground node.

39. The system of claim 37, where the VCO stages are coupled in parallel between a negative voltage supply and a regulated supply node.

40. The system of claim 39, where the VCO current is produced by a VCO current source that is biased by the biasing signal, and where the VCO current source is coupled in series between a positive voltage supply and the regulated supply node.

41. The system of claim 30, where the charge pump system and voltage controlled oscillator are configured to be driven at least partially in response to application of a shared biasing signal which is generated based on detected differences between the output signal and the desired characteristic, and where the biasing signal is coupled into the charge pump system via an isolated input path configured to inhibit undesired signal coupling from the charge pump system to the voltage controlled oscillator via the shared biasing signal.

42. The system of claim 41, where the isolated input path includes a current mirror configured to produce a mirrored copy of the biasing signal for use within the charge pump system.

43. The system of claim 41, further comprising a bias generator configured to dynamically generate the biasing signal free of any predetermined external bias.

44. The system of claim 41, where the biasing signal is generated by a bias generator that matches an effective impedance of the voltage controlled oscillator so that current supplied to the voltage controlled oscillator is substantially independent of supply and substrate noise.

45. The system of claim 30, further comprising a bias generator configured to generate a biasing signal via operation of a feedback loop responsive to currents generated by the charge pump system, where the voltage controlled oscillator is configured to produce the output signal in response to application of the biasing signal,

and where charge pump output is applied to the bias generator along a proportional control path and an integrating control path, the proportional control path including a current mirror isolation mechanism to prevent capacitance on the proportional control path from affecting dynamic response of the bias generator feedback loop.

46. The system of claim 30, where the higher-current charge pump is configured to deliver charge pump currents that are at least an order of magnitude higher than those delivered by the other charge pump.