Reconfigurable, multi-output frame grabber for machine vision applications

• US 20040135907A1
• Filed: 01/09/2003
• Published: 07/15/2004
• Est. Priority Date: 01/09/2003
• Status: Active Grant

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Inventors: Krohn, Robert M., Pratt, Steven J.
• Granted Patent: US 7,391,451 B2
• Time in Patent Office: Days
• US Class Current: 348/254
• CPC Class Codes: G06V 10/20 Image preprocessing

Abstract

An apparatus processes a video image. The apparatus includes an imaging device, a frame grabber device, and a host computer. The imaging device (20) produces a gray level image representing the video image. The frame grabber device conducts preprocessing functions on the gray level image and produces a plurality of image types from the gray level image. The host computer has a memory for storing the plurality of image types. The plurality of image types are transferred directly from the frame grabber device to the memory of the host computer.

Claims

1. An apparatus for processing a video image, said apparatus comprising:

an imaging device for producing a gray level image representing the video image;

a frame grabber device for conducting preprocessing functions on the gray level image and for producing a plurality of image types from the gray level image; and

a host computer having a memory for storing the plurality of image types, the plurality of image types being transferred directly from said frame grabber device to said memory of said host computer.

2. The apparatus as set forth in claim 1 wherein said frame grabber device includes a reformatting module for converting the video image to a common format internal to said frame grabber device.

3. The apparatus as set forth in claim 2 wherein said frame grabber device includes a processing module for converting the video image to multiple unique representations.

4. The apparatus as set forth in claim 3 wherein said frame grabber device includes an arbitrating module for converting parallel signals from said processing module to a serial signal.

5. The apparatus as set forth in claim 4 wherein said frame grabber device includes a dual-port random access memory (DP-RAM) module for providing a buffer between said arbitrating module and said host computer.

6. The apparatus as set forth in claim 5 wherein said frame grabber device includes a local microprocessor for controlling the functioning of said frame grabber device.

7. The apparatus as set forth in claim 6 wherein said frame grabber device includes a synchronous random access memory (SRAM) module for storing address information.

8. The apparatus as set forth in claim 1 further including a host computer interface (HCI) bridge for providing communication between a local bus on said frame grabber device and a host computer interface bus on said host computer.

9. The apparatus as set forth in claim 1 wherein said frame grabber device includes a flash programmable read only memory (Flash PROM) for storing code and configuration data in a non-volatile manner.

10. The apparatus as set forth in claim 1 wherein said frame grabber device monitors and controls the transfer of the plurality of image types from said frame grabber device to said memory of said host computer.

11. A method for processing a video image, said method comprising the steps of:

capturing a first gray level image from the video image;

processing the first gray level image during said capturing step, said processing step including the step of generating multiple images from the first image; and

transferring data representing the first image and the multiple images directly to the memory of a host computer,

said processing step being conducted by a field programmable gate array, the field programmable gate array being located physically apart from the host computer.

12. The method as set forth in claim 11 further including the step of transferring the data representing the first image and the multiple images from the memory of the host computer to a central processing unit of the host computer.

13. The method as set forth in claim 11 further including the step of converting the first image and the multiple images from multiple parallel signals to a single serial signal.

14. The method as set forth in claim 11 further including the step of monitoring the functioning of the field programmable gate array by the host computer.

15. The method as set forth in claim 11 further including the step of reformatting the video image to a common format internal to the field programmable gate array.

16. An image processing system comprising:

a camera for electronically capturing a physical image;

a frame grabber for processing the physical image and producing multiple data streams representing the physical image; and

a host computer having a memory for storing the data from the multiple data streams, said frame grabber serially transferring the multiple data streams directly to said memory of said host computer.

17. The image processing system as set forth in claim 16 wherein said frame grabber includes a reformatting module for converting the physical image to a common format internal to said frame grabber, a processing module for deriving a data set from the physical image, and an arbitrating module for converting the multiple data streams to an equivalent single serial data stream.

18. The image processing system as set forth in claim 16 wherein said frame grabber includes an arbitrating module for conducting first-in-first-out (FIFO) storage of the multiple data streams.

19. The image processing system as set forth in claim 16 wherein said frame grabber includes a field programmable gate array for allowing reconfiguration of said frame grabber without changing the physical hardware of said frame grabber.

20. The image processing system as set forth in claim 16 wherein said frame grabber comprises a control card for connecting to a processor of said host computer.