Integrated displays using nanowire transistors
First Claim
1. An active matrix backplane used within a display, comprising:
- a plurality of pixels; and
a plurality of pixel transistors, wherein a pixel transistor within said plurality of pixel transistors controls a corresponding pixel within said plurality of pixels, wherein each pixel transistor within said plurality of pixel transistors is a nanowire transistor.
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Abstract
The present invention is directed to a display using nanowire transistors. In particular, a liquid crystal display using nanowire pixel transistors, nanowire row transistors, nanowire column transistors and nanowire edge electronics is described. A nanowire pixel transistor is used to control the voltage applied across a pixel containing liquid crystals. A pair of nanowire row transistors is used to turn nanowire pixel transistors that are located along a row trace connected to the pair of nanowire row transistors on and off. Nanowire column transistors are used to apply a voltage across nanowire pixel transistors that are located along a column trace connected to a nanowire column transistor. Displays including organic light emitting diodes (OLED) displays, nanotube field effect displays, plasma displays, micromirror displays, micoelectromechanical (MEMs) displays, electrochromic displays and electrophoretic displays using nanowire transistors are also provided.
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Citations
53 Claims
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1. An active matrix backplane used within a display, comprising:
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a plurality of pixels; and
a plurality of pixel transistors, wherein a pixel transistor within said plurality of pixel transistors controls a corresponding pixel within said plurality of pixels, wherein each pixel transistor within said plurality of pixel transistors is a nanowire transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A liquid crystal display having a base substrate comprising:
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(a) a plurality of pixels;
(b) a plurality of pixel transistors, wherein a pixel transistor within said plurality of pixel transistors controls a corresponding pixel within said plurality of pixels;
(c) a plurality of column transistors, wherein a column transistor within said plurality of column transistors applies a voltage across a subset of said plurality of pixel transistors; and
(d) a plurality of row transistors, wherein at least two row transistors within said plurality of row transistors turns a corresponding pixel transistor on and off, wherein at least one of said plurality of pixel transistors, said plurality of column transistors, and said plurality of row transistors are nanowire transistors. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
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50. An nanowire pixel transistor, comprising:
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(a) at least one nanowire, (b) a row electrode that connects said at least one nanowire to a row trace;
(c) a gate electrode that connects said at least one nanowire to a column line trace; and
(d) a pixel electrode that connects said at least one nanowire to conductive material used to apply a voltage across a pixel. - View Dependent Claims (51)
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52. An active matrix backplane used within a display, comprising:
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a plurality of pixels;
a plurality of amorphous silicon pixel transistors, wherein a pixel transistor within said plurality of pixel transistors controls a corresponding pixel within said plurality of pixels; and
a plurality of column transistors, wherein a column transistor within said plurality of column transistors applies a voltage across a subset of said plurality of pixel transistors, and wherein each column transistor within said plurality of pixel transistors is a nanowire transistor. - View Dependent Claims (53)
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Specification