Semiconductor die including conductive columns

• US 20040137724A1
• Filed: 12/22/2003
• Published: 07/15/2004
• Est. Priority Date: 06/15/2001
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Joshi, Rajeev, Wu, Chung-Lin
• Granted Patent: US 7,022,548 B2
• Time in Patent Office: Days
• US Class Current: 438/672
• CPC Class Codes: H01L 2224/03442 using a powder
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05559 non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11464 Electroless plating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11901 : with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/11902 : Multiple masking steps
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides

Abstract

A method for processing a semiconductor substrate is disclosed. The method includes providing a mask having an aperture on a semiconductor substrate having a conductive region. An aperture in the mask is disposed over the conductive region. A pre-formed conductive column is placed in the aperture and is bonded to the conductive region.

Claims

1. A method for forming a semiconductor die package, the method comprising:

a) providing a mask having an aperture on a semiconductor substrate, wherein a conductive region is on the semiconductor substrate and the aperture in the mask is disposed over the conductive region;

b) placing a pre-formed conductive column within the aperture; and

c) bonding the preformed conductive column to the conductive region, wherein the pre-formed conductive column has substantially the same shape before and after bonding.

2. The method of claim 1 wherein the aperture in the mask is a second aperture, and wherein the method further comprises, before a):

d) forming a passivation layer having a first aperture on the semiconductor substrate, and wherein during b), the first aperture is over the conductive region and is aligned with the second aperture in the mask.

3. The method of claim 1 wherein the pre-formed conductive column comprises (i) a copper columnar body and a coating on the copper columnar body, or (ii) a solder column comprising PbSn.

4. The method of claim 1 wherein after bonding, the bonded conductive column has substantially the same shape before the pre-formed conductive column was bonded to the conductive region.

5. The method of claim 1 further comprising:

d) depositing solder paste comprising a flux within the aperture in the mask, between a) and b).

6. The method of claim 1 wherein the pre-formed conductive column comprises (i) a copper columnar body and a coating on the copper columnar body, (ii) a solder column comprising PbSn, or (iii) a lead-free solder column.

7. The method of claim 1 wherein the mask comprises a mesh mask.

8. The method of claim 1 wherein the pre-formed conductive column comprises a columnar body comprising copper, and a layer of solder on the columnar body.

9. The method of claim 1 wherein the conductive column has the shape of a straight column or has a head and a stem.

10. A semiconductor die package made according to the method of claim 1.

11. A method for forming a semiconductor die package, the method comprising:

a) forming a passivation layer comprising a first aperture on a conductive region on a semiconductor substrate, wherein the aperture in the mask is disposed over the conductive region;

b) forming an adhesion layer on the passivation layer and on the conductive region;

c) forming a seed layer on the adhesion layer;

d) forming a patterned photoresist layer comprising a second aperture on the passivation layer, wherein the second aperture is over the conductive region and is aligned with the first aperture;

e) electroplating a conductive layer within the second aperture and on the seed layer;

f) depositing solder paste containing a flux within the second aperture and on the electroplated conductive layer;

g) inserting a pre-formed conductive column into the second aperture;

h) placing the pre-formed conductive column on the conductive layer within the second aperture;

i) removing the patterned photoresist layer;

j) etching portions of the adhesion layer and the seed layer disposed around the bonded pre-formed conductive column; and

k) heating the solder paste to bond the pre-formed conductive column to the conductive region on the semiconductor substrate.

12. The method of claim 11 wherein the conductive column comprises a conductive columnar body having a coating on the columnar body.

13. The method of claim 11 wherein semiconductor substrate comprises a vertical metal oxide field effect transistor (MOSFET) device.

14. A method for forming a semiconductor die package, the method comprising:

a) forming a mask comprising an aperture disposed over a conductive region on a semiconductor substrate, wherein the aperture is disposed over the conductive region;

b) plating a conductive column within the second aperture and on the conductive region; and

c) removing the mask from the semiconductor substrate.

15. The method of claim 14 wherein the conductive column comprises copper.

16. The method of claim 14 wherein plating comprises electroplating.

17. A semiconductor die package made according to the process of claim 14.

18. A semiconductor die package comprising:

a) a semiconductor die;

b) a conductive region on the semiconductor substrate;

c) a passivation layer comprising an aperture on the semiconductor substrate, wherein the aperture is disposed over the conductive region; and

d) a pre-formed, conductive column comprising a lead-free, conductive columnar body and a coating on a conductive columnar body.

19. The semiconductor die package of claim 18 wherein the semiconductor die comprises a power metal oxide semiconductor field effect transistor (MOSFET) device.

20. The semiconductor die package of claim 18 wherein the pre-formed conductive column comprises a copper columnar body and an underbump metallurgy layer on the columnar body.

21. The semiconductor die package of claim 18 wherein the pre-formed conductive column comprises a copper columnar body and wherein the coating comprises solder.

22. The semiconductor die package of claim 18 at least a portion of the coating is on a side region of the conductive columnar body.