Method and apparatus for detecting an unused state in a semiconductor circuit

• US 20040138841A1
• Filed: 01/09/2003
• Published: 07/15/2004
• Est. Priority Date: 01/09/2003
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Hollmer, Shane
• Granted Patent: US 7,155,357 B2
• Time in Patent Office: Days
• US Class Current: 702/82
• CPC Class Codes: G01R 31/31719 Security aspects, e.g. preventing unauthorised access during test
• CPC Class Codes: G06F 11/2247 Verification or detection of system hardware configuration
• CPC Class Codes: G11C 2029/0407 on power on
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

An unused state detection circuit is disclosed that detects an unused state in a semiconductor circuit. A semiconductor circuit is “unused” when the unused state detection circuit has not been permanently cleared. When a semiconductor circuit is first powered up, the unused state detection circuit will detect that the semiconductor circuit has not previously been “used” and can automatically activate a boot up procedure or a testing procedure (or both). After the semiconductor circuit is used, the unused state detection circuit provides an indication that the semiconductor circuit is no longer unused. The unused state detection circuit uses the state of a dedicated non-volatile memory array or a dedicated region of the general non-volatile memory portion of the semiconductor circuit to detect whether the semiconductor circuit has been previously unused.

Claims

1. A semiconductor circuit, comprising:

a processor for executing one or more instructions;

a memory device; and

a circuit for detecting whether said semiconductor circuit is unused.

2. The semiconductor circuit of claim 1, further comprising means for ensuring said unused state is permanently cleared once said semiconductor circuit has been initialized.

3. The semiconductor circuit of claim 1, wherein said circuit initiates a testing of said semiconductor circuit in response to said detection of said unused state.

4. The semiconductor circuit of claim 1, wherein said circuit initiates an initialization of said semiconductor circuit in response to said detection of said unused state.

5. The semiconductor circuit of claim 4, further comprising an external interface for receiving a plurality of instructions for initializing said semiconductor circuit.

6. The semiconductor circuit of claim 1, wherein said circuit uses a state of a non-volatile memory array to detect whether said semiconductor circuit is unused.

7. The semiconductor circuit of claim 1, wherein said circuit comprises a dedicated mini-array of non-volatile memory cells for use in unused detection.

8. The semiconductor circuit of claim 7, wherein said dedicated mini-array of non-volatile memory cells includes at least two active bit lines, blprg and bler, corresponding to program and erase, and wherein said first bit line, blprg, is only programmable and said second bit line, bler, is only eraseable.

9. The semiconductor circuit of claim 8, wherein said cells in said dedicated mini-array of non-volatile memory are initially in approximately a same state and wherein said unused state is detected by sensing said at least two active bit lines, blprg and bler.

10. The semiconductor circuit of claim 8, wherein an offset current is added to one of said at least two active bit lines, blprg and bler, to detect when said semiconductor circuit is first used.

11. The semiconductor circuit of claim 1, wherein said memory device is a non-volatile memory array and wherein said circuit comprises a dedicated region of said non-volatile memory array.

12. The semiconductor circuit of claim 11, wherein one or more dedicated bytes in said dedicated region are compared to a reference current.

13. The semiconductor circuit of claim 12, wherein said one or more dedicated bytes in said dedicated region are in a neutral state when said semiconductor circuit is unused and wherein a used state of said semiconductor circuit is detected by evaluating a current generated by said one or more dedicated bytes.

14. The semiconductor circuit of claim 11, wherein one or more dedicated bytes in said dedicated region are compared to a predefined pattern.

15. The semiconductor circuit of claim 11, wherein one or more dedicated bytes in said dedicated region can be erased but never programmed to indicate a used state.

16. The semiconductor circuit of claim 14, wherein said one or more dedicated bytes in said dedicated region have a uniform pattern that does not match a predefined pattern until said semiconductor circuit has been used.

17. The semiconductor circuit of claim 1, wherein said circuit further comprises a plurality of said circuits for detecting whether said semiconductor circuit is unused, each of said plurality of circuits having an output and further comprising an OR gate to determine whether said semiconductor circuit is unused.

18. A method of testing a semiconductor circuit, said method comprising the steps of:

detecting whether said semiconductor circuit has been previously unused; and

initiating a testing of said semiconductor circuit in response to said detecting step.

19. The method of claim 18, further comprising the step of ensuring said unused state is cleared once said semiconductor circuit has been tested.

20. The method of claim 18, wherein said detecting step further comprises the step of evaluating a circuit indicating whether said semiconductor circuit is unused.

21. The method of claim 18, wherein said detecting step further comprises the step of evaluating an unused state detection circuit embedded on said semiconductor circuit.

22. A method of initializing a semiconductor circuit, said method comprising the steps of:

detecting whether said semiconductor circuit has been previously unused; and

initializing said semiconductor circuit in response to said detecting step.

23. The method of claim 22, further comprising the step of ensuring said unused state is cleared once said semiconductor circuit has been iniatialized.

24. The method of claim 22, wherein said detecting step further comprises the step of evaluating a circuit indicating whether said semiconductor circuit is unused.

25. The method of claim 22, further comprising the step of receiving a plurality of instructions for initializing said semiconductor circuit from an external interface.

26. The method of claim 22, wherein said detecting step further comprises the step of evaluating an unused state detection circuit embedded on said semiconductor circuit.