Routing of interconnected regions

• US 20040139216A1
• Filed: 09/26/2003
• Published: 07/15/2004
• Est. Priority Date: 09/27/2002
• Status: Abandoned Application

• Current Assignee: Zuken Incorporated
• Original Assignee: Zuken Incorporated
• Inventors: Greene, Michael Thomas
• Application Number:
  US10/672,186
• Publication Number:
  US 20040139216A1
• Time in Patent Office: Days
• US Class Current: 709/232
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method is disclosed of determining the routing of interconnected regions of a routing problem by considering all required connections in parallel and only attempting to resolve conflicts when at least some relevant contextual information has been assembled.

Claims

1. A method of determining the routing of interconnected regions of a routing problem by considering all required connections in parallel and only attempting to resolve conflicts when at least some relevant contextual information has been assembled.

2. A method according to claim 1, wherein resolving of conflicts is only attempted when all possible relevant contextual information has been assembled.

3. A method according to claim 1, comprising the steps of:

(a) defining, for each set of regions to be connected, routing which represents a suitable manner of connecting them, respecting only those conflicts which have been explicitly registered with the set currently being considered;

(b) collating all such proposed routing and resolving any conflicts in a symmetric manner;

(c) registering such conflicts with the sets of regions which will be required to respect them on the next pass;

(d) repeating steps (a) to (c) until a sufficient completion and quality of routing solution is attained; and

(e) converting the routing into suitable geometric representations of routing paths in a way which takes all desired routing into account symmetrically and simultaneously.

4. A method according to claim 3, in which the regions are polygons and the shared boundaries are edges.

5. A method according to claim 1, wherein the interconnected regions are regions of an electrical circuit.