Synchronous content addressable memory

• US 20040139276A1
• Filed: 12/22/2003
• Published: 07/15/2004
• Est. Priority Date: 10/30/1997
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Bindiganavale S. Nataraj, Sandeep Khanna, Varadarajan Srinivasan
• Inventors: Nataraj, Bindiganavale S., Khanna, Sandeep, Srinivasan, Varadarajan
• Granted Patent: US 6,961,810 B2
• Time in Patent Office: Days
• US Class Current: 711/108
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A CAM device to perform in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction; (3) perform the comparison of the comparand data with a first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

Claims

1. A method of reading data from a synchronous content addressable memory (CAM) device, comprising the steps of:

instructing the CAM device to compare comparand data with data stored in a plurality of first CAM cells;

comparing the comparand data with the data stored in each of the plurality of first CAM cells;

sensing data stored in a second CAM cell; and

outputting the sensed data from the CAM device, wherein the instructing, comparing, sensing, and outputting steps all occur in one clock cycle.