Hardware-enabled instruction tracing

• US 20040139305A1
• Filed: 01/09/2003
• Published: 07/15/2004
• Est. Priority Date: 01/09/2003
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Starke, William John, Arimilli, Ravi Kumar, Guthrie, Guy Lynn, Cargnoni, Robert Alan
• Application Number:
  US10/339,727
• Publication Number:
  US 20040139305A1
• Time in Patent Office: Days
• US Class Current: 712/227
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/3808 for instruction reuse, e.g. trace cache, branch target cache
• CPC Class Codes: G06F 9/3812 with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification

Abstract

A data processing system includes an instruction pipeline, including one or more execution units that execute instructions and an instruction sequencing unit that dispatches instructions to the execution units for execution. The data processing system further includes a memory controller for a memory containing an instruction trace log and an interconnect coupled to the instruction pipeline and to the memory controller. The interconnect transmits to the memory controller for storage in the instruction trace log instructions processed within the instruction pipeline.

Claims

1. A data processing system, comprising:

an instruction pipeline, including;

one or more execution units that execute instructions;

an instruction sequencing unit coupled to said one or more execution units, wherein said instruction sequencing unit dispatches instructions to said execution units for execution;

a memory controller for a memory containing an instruction trace log; and

an interconnect coupled to said instruction pipeline and to said memory controller, wherein said interconnect transmits to said memory controller for storage in said instruction trace log instructions processed within said instruction pipeline.

2. The data processing system of claim 1, wherein said instructions transmitted to said memory controller for storage in said instruction trace log comprise each instruction dispatched by said instruction sequencing unit.

3. The data processing system of claim 1, wherein said instructions transmitted to said memory controller for storage in said instruction trace log comprise only completed instructions.

4. The data processing system of claim 1, wherein said data processing system employs a plurality of instruction types, and wherein said instruction sequencing unit transmits to said memory controller for storage in said instruction trace log only instructions belonging to selected ones of said plurality of instruction types.

5. The data processing system of claim 1, wherein said memory controller and said instruction pipeline are integrated within an integrated circuit chip, and wherein said interconnect comprises a bus integrated within said integrated circuit chip.

6. The data processing system of claim 5, wherein said integrated circuit chip comprises a first integrated circuit chip, said data processing system further comprising:

a system interconnect coupled to said first integrated circuit chip;

at a second integrated circuit chip coupled to said system interconnect; and

the memory coupled to said memory controller, wherein the memory includes a private memory area containing said instruction trace log that is accessible only by requests originating from the first integrated circuit chip.

7. A method of operating a processor, said method comprising:

processing instructions within an instruction pipeline including one or more execution units and an instruction sequencing unit that dispatches instructions to said execution units for execution;

transmitting from said instruction pipeline to a memory controller selected instructions processed within said instruction pipeline; and

the memory controller storing in an instruction trace log within a memory the selected instructions processed within said instruction pipeline.

8. The method of claim 7, wherein said transmitting comprises transmitting to said memory controller for storage in said instruction trace log each instruction dispatched by said instruction sequencing unit.

9. The method of claim 7, wherein said transmitting comprises transmitting to said memory controller for storage in said instruction trace log only completed instructions.

10. The method of claim 7, wherein said processor employs a plurality of instruction types, and wherein said transmitting comprises transmitting to said memory controller for storage in said instruction trace log only instructions belonging to selected ones of said plurality of instruction types.

11. The method of claim 7, wherein said memory controller and said instruction pipeline are integrated within an integrated circuit chip, and wherein said transmitting comprises transmitting said selected instructions via a bus integrated within said integrated circuit chip.

12. The method of claim 11, wherein said storing comprises storing said instruction trace log within a private memory area accessible only by requests originating from the integrated circuit chip.