Method and apparatus for responding to access errors in a data processing system

• US 20040139372A1
• Filed: 01/09/2003
• Published: 07/15/2004
• Est. Priority Date: 01/09/2003
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William C., Millar, Brian M., Fitzsimmons, Michael D., Vaglica, John J.
• Granted Patent: US 7,278,062 B2
• Time in Patent Office: Days
• US Class Current: 714/43
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error response circuitry (12), each coupled to the bus (58, 60). The access error detection circuitry detects an access error in the data processing system. The access error response circuitry initiates replacement of an existing value on the bus with a predetermined value when the access error has been detected, and continues to replace the existing value on the bus with the predetermined value when the access error has been detected and a persistent mode indicator has been asserted. The predetermined value may correspond to a predetermined instruction value (74) or a predetermined data value (76). In one embodiment, different values for the predetermined value may be used depending on the current operating mode of the data processing system.

Claims

1. A data processing system having a processor coupled to a bus, the data processing system comprising:

access error detection circuitry, coupled to the bus, the access error detection circuitry detecting an access error in the data processing system; and

access error response circuitry, coupled to the bus, the access error response circuitry initiating replacement of an existing value on the bus with a predetermined value when the access error has been detected, and the access error response circuitry continuing to replace the existing value on the bus with the predetermined value when the access error has been detected and a first indicator has been asserted.

2. A data processing system as in claim 1, wherein the access error response circuitry stops replacing the existing value on the bus with the predetermined value when a second indicator is received.

3. A data processing system as in claim 2, wherein the second indicator indicates that an interrupt vector fetch has been initiated by the processor.

4. A data processing system as in claim 1, wherein the predetermined value is selected to be one of a plurality of values based upon which one of a plurality of modes has been selected for the data processing system.

5. A data processing system as in claim 1, wherein the predetermined value corresponds to a software interrupt instruction.

6. A data processing system as in claim 1, wherein the predetermined value corresponds to an undefined Java bytecode.

7. A data processing system as in claim 1, wherein the predetermined value has a selectable bit-ordering, and wherein the selectable bit-ordering is one of big endian and little endian.

8. A data processing system as in claim 1, wherein if the access error occurs on a write access, the write access is blocked.

9. A data processing system as in claim 1, wherein if the bus transfers data and the access error occurs on a read access, then the predetermined value is a predetermined data value.

10. A data processing system as in claim 1, further comprising:

a cache, coupled to the processor;

wherein the predetermined value instead of the existing value is stored in the cache.

11. A data processing system as in claim 9, further comprising:

a data cache, coupled to the processor;

wherein the predetermined data value instead of the existing value is stored in the data cache.

12. A data processing system as in claim 9, wherein the predetermined data value is all zeros.

13. A data processing system, comprising:

a processor;

an instruction bus;

a data bus;

an instruction cache, coupled to the instruction bus;

a data cache, coupled to the data bus;

access error detection circuitry, coupled to the instruction bus and to the data bus, the access error detection circuitry detecting an access error in the data processing system; and

access error response circuitry, coupled to the instruction bus and to the data bus, the access error response circuitry initiating replacement of an existing instruction value on the instruction bus with a predetermined instruction value when the access error has been detected, said access error response circuitry continuing to replace the existing instruction value on the instruction bus with the predetermined instruction value when the access error has been detected and a first indicator has been asserted.

14. A data processing system as in claim 13, wherein the access error response circuitry stops replacing the existing instruction value on the instruction bus with the predetermined instruction value when a second indicator is received.

15. A data processing system as in claim 13, wherein said access error response circuitry initiates replacement of an existing data value on the data bus with a predetermined data value when the access error has been detected and the access error occurs on a read access, and wherein the predetermined data value instead of the existing data value is stored in the data cache.

16. A data processing system as in claim 13, wherein if the access error occurs on a write access, the write access is blocked.

17. A data processing system as in claim 13, wherein the predetermined instruction value is selected to be one of a plurality of values based upon which one of a plurality of modes has been selected for the data processing system.

18. A data processing system as in claim 17, wherein the predetermined instruction value corresponds to a software interrupt instruction for a first one of the plurality of modes.

19. A data processing system as in claim 17, wherein the predetermined instruction value corresponds to an undefined Java bytecode for a second one of the plurality of modes.

20. A method for responding to an access error in a data processing system, comprising:

detecting an access error in the data processing system;

determining which one of a plurality of modes is a current mode of the data processing system;

replacing an existing bus value with a predetermined value when the access error is detected,

wherein the predetermined value has a first value if the current mode of the data processing system is a first one of the plurality of modes, and wherein the predetermined value has a second value if the current mode of the data processing system is a second one of the plurality of modes, and wherein the first value and the second value are not a same value.

21. A method as in claim 20, wherein the predetermined value is used to determine a software processing routine to be executed in the data processing system.

22. A method as in claim 20, wherein the first value corresponds to a software interrupt instruction.

23. A method as in claim 20, wherein the second value corresponds to a Java bytecode.