Semiconductor devices and methods for fabricating the same

• US 20040140518A1
• Filed: 12/26/2003
• Published: 07/22/2004
• Est. Priority Date: 12/30/2002
• Status: Active Grant

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Lee, Ki-Min
• Granted Patent: US 6,958,278 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

Semiconductor devices having a dual gate and method for fabricating the same are disclosed. A disclosed example method comprises: forming dummy gates in a semiconductor substrate; sequentially forming a lightly doped drain (LDD) region, a spacer and a source/drain; depositing an insulation film above the semiconductor substrate; exposing the dummy gates by planarizing the insulation film; removing the dummy gates; selectively injecting impurities into a region associated with at least one of the removed dummy gates; forming gate oxide films having different thicknesses on the regions associated with the removed dummy gates; depositing a polysilicon layer above the gate oxide films; and then forming polysilicon gates by planarizing the polysilicon layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having device isolation regions; and

transistors provided between the device isolation regions, each of the transistors including a gate oxide film and a polysilicon gate;

wherein the gate oxide films of at least one of the transistors has a thickness different from that of the gate oxide films of remaining ones of the transistors, and the gate oxide films of the transistors surround corresponding ones of the polysilicon gates on all sides except for a top of the polysilicon gate.

2. A method for fabricating a semiconductor device, comprising:

forming first and second dummy gates in a semiconductor substrate;

forming a lightly doped drain (LDD), a spacer and a source/drain;

depositing an insulation film above the semiconductor substrate;

exposing the first and second dummy gates by planarizing the insulation film;

removing the first and second dummy gates;

selectively injecting impurities into a region associated with the first dummy gate;

forming a first gate oxide film having a first thickness in the region associated with the first dummy gate and forming a second gate oxide film having a second thickness in a region associated with the second dummy gate, the first thickness being different than the second thickness;

depositing a polysilicon layer above the gate oxide films; and

forming first and second polysilicon gates by planarizing the polysilicon layer.

3. A method as defined in claim 2, wherein forming the first and second dummy gates further comprises depositing a film formed of inorganic material such as silicon nitride (SiN) and patterning the deposited film.

4. A method as defined in claim 3, wherein patterning the deposited film comprises exposure and development processes using a photoresist.

5. A method as defined in claim 3, wherein a wet etching process using hot phosphoric acid is used in removing the first and second dummy gates.

6. A method as defined in claim 3, wherein the impurities comprise one selected from a group consisting of As, P and Sb.

7. A method as defined in claim 3, wherein at least one of a chemical mechanical polishing (CMP) method and an etch back method is used to planarize at least one of the insulation film and the polysilicon layer.

8. A method as defined in claim 2, wherein forming the first and second dummy gates further comprises depositing a film formed of organic material and patterning the deposited film.

9. A method as defined in claim 8, wherein the deposited film comprises polyimide

10. A method as defined in claim 8, wherein patterning the deposited film comprises exposure and development processes using a photoresist.

11. A method as defined in claim 8, wherein removing the first and second dummy gates comprises an oxygen (O₂) plasma ashing process.

12. A method as defined in claim 8, wherein the impurities comprises one selected from a group consisting of As, P and Sb.

13. A method as defined in claim 8, wherein at least one of a chemical mechanical polishing (CMP) method and an etch back method is used to planarize at least one of the insulation film and the polysilicon.