Non-volatile flip flop

• US 20040141363A1
• Filed: 01/09/2004
• Published: 07/22/2004
• Est. Priority Date: 04/10/2002
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Tanaka, Hideyuki, Ohtsuka, Takashi
• Granted Patent: US 7,206,217 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 14/0072 and the nonvolatile element is a ferroelectric element
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

A non-volatile flip flop according to the invention comprising: a flip flop section (4) having a pair of memory nodes (5, 6) for storing a pair of inverse logic data elements; and a pair of non-volatile resistance change elements (11, 12) which are connected to the pair of memory nodes (5, 6) through switching elements (9, 10) respectively and the resistances of which vary so as to be retainable, wherein, in a store operation, the resistances of the pair of non-volatile resistance change elements (11, 12) can be varied according to the respective potentials of the pair of memory nodes (5, 6) and, in a recall operation, the pair of memory nodes (5, 6) can be placed at potentials respectively according to the difference in resistance between the pair of non-volatile resistance change elements (11, 12).

Claims

1. A non-volatile flip flop comprising:

a flip flop section having a pair of memory nodes for storing a pair of inverse logic data elements; and

a pair of non-volatile resistance change elements which are connected to the pair of memory nodes respectively and the resistances of which vary so as to be retainable;

wherein, in a store operation, the resistances of the pair of non-volatile resistance change elements can be varied according to the respective potentials of the pair of memory nodes and, in a recall operation, the pair of memory nodes can be placed at potentials respectively according to the difference in resistance between the pair of non-volatile resistance change elements.

2. The non-volatile flip flop according to claim 1,

wherein, in the store operation, either of the pair of non-volatile resistance change elements is brought into a high resistance state whereas the other is brought into a low resistance state according to the respective potentials of the pair of memory nodes;

and

wherein, in the recall operation, either of the pair of memory nodes is placed at a high potential whereas the other is placed at a low potential according to the difference in resistance between the pair of non-volatile resistance change elements.

3. The non-volatile flip flop according to claim 2,

wherein the pair of non-volatile resistance change elements are made from a phase change material which is in a high resistance state when it is in an amorphous state and is in a low resistance state when it is in a crystalline state.

4. The non-volatile flip flop according to claim 3,

wherein, in the store operation, either of the pair of non-volatile resistance change elements is in the amorphous state while the other being in the crystalline state.

5. The non-volatile flip flop according to claim 4,

wherein a pair of switching elements are sandwiched between the pair of memory nodes and the pair of non-volatile resistance change elements;

wherein the pair of non-volatile resistance change elements are connected to a plate line;

wherein either of the pair of memory nodes is at a high potential while the other being at a low potential; and

wherein by turning the pair of switching elements ON to cause a potential difference between the pair of memory nodes and the plate line, either of the pair of non-volatile resistance change elements is brought into the amorphous state and the other is brought into the crystalline state.

6. The non-volatile flip flop according to claim 5,

wherein after both of the pair of non-volatile resistance change elements are brought into the amorphous state by causing a potential difference between the pair of memory nodes and the plate line, the state of either of the pair of non-volatile resistance change elements is changed to the crystalline state, whereby either of the pair of non-volatile resistance change elements is brought into the amorphous state while the other is brought into the crystalline state.

7. The non-volatile flip flop according to claim 6,

wherein a potential difference is produced between both ends of the other non-volatile resistance change element sandwiched between the other memory node maintained at a low potential and the plate line by applying a high potential voltage to the plate line, while the other non-volatile resistance change element is brought into the amorphous state by applying a voltage having a high pulse width to the other non-volatile resistance change element;

and

a potential difference is produced between both ends of the one non-volatile resistance change element sandwiched between the one memory node maintained at a high potential and the plate line by applying a low potential voltage to the plate line, while the one non-volatile resistance change element is brought into the amorphous state by applying a voltage having a high pulse width to the one non-volatile resistance change element;

whereby the pair of non-volatile resistance change elements are both brought into the amorphous state.

8. The non-volatile flip flop according to claim 6,

wherein a potential difference is produced between both ends of the one non-volatile resistance change element sandwiched between the one memory node maintained at a high potential and the plate line by applying a low potential voltage to the plate line, while the one non-volatile resistance change element is brought into the amorphous state by applying a voltage having a high pulse width to the one non-volatile resistance change element;

and

a potential difference is produced between both ends of the other non-volatile resistance change element sandwiched between the other memory node maintained at a low potential and the plate line by applying a high potential voltage to the plate line, while the other non-volatile resistance change element is brought into the amorphous state by applying a voltage having a high pulse width to the other non-volatile resistance change element;

whereby the pair of non-volatile resistance change elements are both brought into the amorphous state.

9. The non-volatile flip flop according to claim 6,

wherein a potential difference is produced between both ends of the one of the pair of non-volatile resistance change elements both of which are in the amorphous state, by applying a low potential voltage to the plate line, the one element being sandwiched between the one memory node maintained at a high potential and the plate line, while the one non-volatile resistance change element is brought into the crystalline state by applying a voltage having a low pulse width to the one non-volatile resistance change element, whereby the state of either of the pair of non-volatile resistance change elements is changed to the crystalline state.

10. The non-volatile flip flop according to claim 6,

wherein a potential difference is produced between both ends of the other one of the pair of non-volatile resistance change elements both of which are in the amorphous state, by applying a high potential voltage to the plate line, the other element being sandwiched between the other memory node maintained at a low potential and the plate line, while the other non-volatile resistance change element is brought into the crystalline state by applying a voltage having a low pulse width to the other non-volatile resistance change element, whereby the state of either of the pair of non-volatile resistance change elements is changed to the crystalline state.

11. The non-volatile flip flop according to claim 5,

wherein after both of the non-volatile resistance change elements are brought into the crystalline state by producing a potential difference between the pair of memory nodes and the plate line, the state of either of the pair of non-volatile resistance change elements is changed to the amorphous state, whereby either of the pair of non-volatile resistance change elements is brought into the amorphous state while the other element is brought into the crystalline state.

12. The non-volatile flip flop according to claim 11,

wherein a potential difference is produced between both ends of the other non-volatile resistance change element sandwiched between the other memory node maintained at a low potential and the plate line by applying a high potential voltage to the plate line, while the other non-volatile resistance change element is brought into the crystalline state by applying a voltage having a low pulse width to the other non-volatile resistance change element;

and

a potential difference is produced between both ends of the one non-volatile resistance change element sandwiched between the one memory node maintained at a high potential and the plate line by applying a low potential voltage to the plate line, while the one non-volatile resistance change element is brought into the crystalline state by applying a voltage having a low pulse width to the one non-volatile resistance change element;

whereby the pair of non-volatile resistance change elements are both brought into the crystalline state.

13. The non-volatile flip flop according to claim 11,

wherein a potential difference is produced between both ends of the one non-volatile resistance change element sandwiched between the one memory node maintained at a high potential and the plate line by applying a low potential voltage to the plate line, while the one non-volatile resistance change element is brought into the crystalline state by applying a voltage having a low pulse width to the one non-volatile resistance change element;

and

a potential difference is produced between both ends of the other non-volatile resistance change element sandwiched between the other memory node maintained at a low potential and the plate line by applying a high potential voltage to the plate line, while the other non-volatile resistance change element is brought into the crystalline state by applying a voltage having a low pulse width to the other non-volatile resistance change element;

whereby the pair of non-volatile resistance change elements are both brought into the crystalline state.

14. The non-volatile flip flop according to claim 11,

wherein a potential difference is produced between both ends of the one of the pair of non-volatile resistance change elements both of which are in the crystalline state, by applying a low potential voltage to the plate line, the one element being sandwiched between the one memory node maintained at a high potential and the plate line, while the one non-volatile resistance change element is brought into the amorphous state by applying a voltage having a high pulse width to the one non-volatile resistance change element, whereby the state of either of the pair of non-volatile resistance change elements is changed to the amorphous state.

15. The non-volatile flip flop according to claim 11,

wherein a potential difference is produced between both ends of the other one of the pair of non-volatile resistance change elements both of which are in the crystalline state, by applying a high potential voltage to the plate line, the other element being sandwiched between the other memory node maintained at a low potential and the plate line, while the other non-volatile resistance change element is brought into the amorphous state by applying a voltage having a high pulse width to the other non-volatile resistance change element, whereby the state of either of the pair of non-volatile resistance change elements is changed to the amorphous state.

16. The non-volatile flip flop according to claim 5,

wherein, in the recall operation, the pair of switching elements are turned ON, the potential at the plate line is raised from ground potential to power source potential, and a power source for the flip flop section is turned ON while the pair of switching elements are turned OFF, whereby either of the pair of memory nodes is placed at a high potential while the other memory node is placed at a low potential.

17. The non-volatile flip flop according to claim 1,

wherein the pair of non-volatile resistance change elements respectively have a ferroelectric substance and an MIS transistor whose gate electrode is connected to at least one end of the ferroelectric substance;

and

wherein the polarization of the ferroelectric substances varies according to the potentials at the pair of memory nodes and the resistances of the MIS transistors vary according to the polarization.

18. The non-volatile flip flop according to claim 17,

wherein in each of the pair of non-volatile resistance change elements, the Vt value of the MIS transistor varies according to the polarization of the ferroelectric substance so that the resistance of the MIS transistor varies.

19. The non-volatile flip flop according to claim 18,

wherein, in the store operation, according to the potentials of the pair of memory nodes, the Vt of the MIS transistor of either one of the pair of non-volatile resistance change elements is set to a high Vt value thereby bringing the MIS transistor of the one resistance change element into a high resistance state, while the Vt of the MIS transistor of the other non-volatile resistance change element is set to a low Vt value thereby bringing the MIS transistor of the other resistance change element into a low resistance state;

and

wherein, in the recall operation, either of the pair of memory nodes is placed at a high potential while the other memory node is placed at a low potential, according to the difference in resistance between the MIS transistors of the pair of non-volatile resistance change elements.

20. The non-volatile flip flop according to claim 17,

wherein, in the pair of non-volatile resistance change elements, a depletion layer of the MIS transistor varies in thickness according to the polarization of the ferroelectric substance, so that the resistance of the MIS transistor varies.

21. The non-volatile flip flop according to claim 20,

wherein, in the store operation, according to the potentials of the pair of memory nodes, the depletion layer of the MIS transistor of either one of the pair of non-volatile resistance change elements increases in thickness thereby bringing the MIS transistor of the one resistance change element into the high resistance state, while the depletion layer of the MIS transistor of the other non-volatile resistance change element reduces in thickness thereby bringing the MIS transistor of the other resistance change element into the low resistance state;

and

wherein, in the recall operation, either of the pair of memory nodes is placed at a high potential while the other memory node is placed at a low potential, according to the difference in resistance between the MIS transistors of the pair of non-volatile resistance change elements.