Method and apparatus for selecting memory cells within a memory array

• US 20040141393A1
• Filed: 01/21/2003
• Published: 07/22/2004
• Est. Priority Date: 01/21/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Eaton, James Robert, Ku, Joseph
• Granted Patent: US 6,940,770 B2
• Time in Patent Office: Days
• US Class Current: 365/203
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders

Abstract

The invention includes an apparatus and method of selecting memory cells within a memory array. The method includes receiving a memory cell address. A column address and a row address are generated from the memory cell address. Row select lines or column select lines are pre-charged. A self-timed charging circuit is initiated to provide an adequate amount of time to charge a selected row, and to initiate elimination of static current flowing to unselected rows after a self-timed delay. The other of the row select lines or the column select lines are then pre-charged. Memory cells are selected based upon the column address and the row address. One of two states of the memory cells can be based upon sensing threshold voltages of sense lines that correspond with the selected memory cells.

Claims

1. A method of selecting memory cells within a memory array, the method comprising:

receiving a memory cell address;

generating a column address and a row address from the memory cell address;

pre-charging one of row select lines and column select lines;

initiating a delay circuit;

pre-charging an other of the row select lines and the column select lines upon activation by the delay circuit; and

selecting memory cells based upon the column address and the row address.

2. The method of selecting memory cells within a memory array of claim 1, wherein the delay circuit comprises a self-timed select circuit.

3. The method of selecting memory cells within a memory array of claim 1, wherein pre-charging the row select lines comprises:

charging a row charge holding device for each row select line;

dis-charging each row charge holding device if any row address lines associated with the row address is a first voltage potential.

4. The method of selecting memory cells within a memory array of claim 3, wherein each row charge holding device is discharged if the row select line corresponding to the row charge holding device is not selected.

5. The method of selecting memory cells within a memory array of claim 3, wherein the first voltage potential is below a threshold voltage potential.

6. The method of selecting memory cells within a memory array of claim 3, wherein a charging transistor for charging the charge holding device is located on a different substrate than the memory array, and a memory array substrate that comprises the memory array includes passive circuit devices.

7. The method of selecting memory cells within a memory array of claim 1, further comprising:

detecting one of two states of the memory cells based upon sensing threshold voltages of sense lines that correspond with the selected memory cells.

8. The method of selecting memory cells within a memory array of claim 1, wherein the row select lines are word lines.

9. The method of selecting memory cells within a memory array of claim 1, wherein the column select lines are bit lines.

10. The method of selecting memory cells within a memory array of claim 1, wherein a timing delay of the delay circuit estimates a worst case time delay associated with row select lines.

11. The method of selecting memory cells within a memory array of claim 1, wherein initiating the delay circuit comprises:

charging a worst case delay estimate capacitor with a dummy word line select line.

12. The method of selecting memory cells within a memory array of claim 11, wherein the dummy word line is selected upon initiation of access of the memory array.

13. The method of selecting memory cells within a memory array of claim 1, wherein pre-charging the row select lines comprises:

charging charge holding devices corresponding to each of the row select lines;

activating a row select line as a function of charge on a corresponding charge holding device; and

dis-charging corresponding charge holding devices if any of a plurality of address lines electrically connected to the charge holding device are below a first voltage potential.

14. The method of selecting memory cells within a memory array of claim 1, wherein pre-charging the column select lines comprises:

pre-charging charge holding devices corresponding to each of the column select lines;

activating a column select line as a function of charge on a corresponding charge holding device; and

dis-charging corresponding charge holding devices if any of a plurality of address lines electrically connected to the charge holding device are below a first voltage potential.

16. The apparatus for selecting memory cells within a memory array of claim 14, wherein the row select lines are word lines.

17. The apparatus for selecting memory cells within a memory array of claim 14, wherein the column select lines are bit lines.

18. The apparatus for selecting memory cells within a memory array of claim 14, wherein the delay of the delay timing block estimates a worst case time delay associated with the row select lines and the column select lines.

19. The apparatus for selecting memory cells within a memory array of claim 14, wherein the delay timing block comprises a worst case delay estimate capacitor that is connected to a dummy word line, the delay being provided by the worst case delay estimate capacitor being charged.

15. An apparatus for selecting memory cells within a memory array, the apparatus comprising:

a row decoder for activating a row selection;

a column decoder for activating a column selection;

means for charging row charge holding devices that correspond with row select lines;

a delay timing block for providing enough time for the selected row line with a heaviest loading to be charged;

means for charging column charge holding devices that correspond with column select lines to a low voltage potential;

means for dis-charging row charge holding devices that correspond to non-selected row select lines; and

means for charging column charge holding devices that correspond to non-selected column select lines to a high voltage potential.

22. The memory array of claim 15, wherein the delay timing block comprises a worst case delay estimate capacitor that is connected to a dummy word line, the delay being provided by the worst case delay estimate capacitor being charged.

20. A memory array comprising:

an array of memory cells;

a plurality of address lines for addressing the memory cells;

an apparatus for selecting memory cells within a memory array, the apparatus comprising;

a row decoder for activating a row selection;

a column decoder for activating a column selection;

means for charging row charge holding devices that correspond with row select lines;

a delay timing block for providing enough time for the selected row line with a heaviest loading to be charged;

means for charging column charge holding devices that correspond with column select lines to a low voltage potential;

means for dis-charging row charge holding devices that correspond to non-selected row select lines; and

means for charging column charge holding devices that correspond to non-selected column select lines to a high voltage potential.

21. The memory array of claim 20, wherein the delay of the delay timing block estimates a worst case time delay associated with the row select lines.

23. A computing device comprising:

a central processing unit;

a memory array that can be accessed by the central processing unit;

an array of memory cells;

a plurality of address lines for addressing the memory cells;

An apparatus for selecting memory cells within a memory array, the apparatus comprising;

a row decoder for activating a row selection;

a column decoder for activating a column selection;

means for charging row charge holding devices that correspond with row select lines;

a delay timing block for providing enough time for the selected row line with a heaviest loading to be charged;

means for charging column charge holding devices that correspond with column select lines to a low voltage potential;

means for dis-charging row charge holding devices that correspond to non-selected row select lines; and

means for charging column charge holding devices that correspond to non-selected column select lines to a high voltage potential.

24. The computing device of claim 23, wherein the delay of the delay timing block estimates a worst case time delay associated with the row select lines.

25. The computing device of claim 23, wherein the delay timing block comprises a worst case delay estimate capacitor that is connected to a dummy word line, the delay being provided by the worst case delay estimate capacitor being charged.