Hatted polysilicon gate structure for improving salicide performance and method of forming the same

• US 20040142517A1
• Filed: 01/17/2003
• Published: 07/22/2004
• Est. Priority Date: 01/17/2003
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Chih-Wei, Wang, Mei-Yun
• Application Number:
  US10/347,007
• Publication Number:
  US 20040142517A1
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Alternate methods of forming low resistance “hatted” polysilicon gate elements are provided that increase the effective area in the polysilicon gate for silicide grain growth during silicide formation. The expanded top portion helps to prevent silicide agglomeration in the silicide regions, thereby maintaining or reducing electrode resistance, improving high-frequency performance, and reducing gate delay in sub micron FET ULSI devices, without increasing the underlying active channel length.

Claims

1. A method of forming a low resistance salicided gate structure of a field effect transistor, comprising the following steps:

forming a pair of vertical spacers over a substrate, said spacers defining a gate trench region having a gate dielectric layer formed therein;

depositing a blanket layer of polysilicon over said spacers and in said gate trench region;

planarizing said deposited layer of polysilicon;

selectively etching said planarized polysilicon layer to form a polysilicon gate element having a generally trapezoidal shaped polysilicon region over said gate trench, wherein a base of said trapezoidal region at least partially overlaps said spacers; and

forming a silicide contact in said trapezoidal region.

2. The method of claim 1, wherein said silicide formation step includes the step of depositing a refractory metal layer over said trapezoidal shaped polysilicon region and processing said refractory metal layer to form said silicide contact.

3. The method of claim 2, wherein said trapezoidal region is sized to substantially prevent silicide agglomeration in said silicide contact.

4. The method of claim 3, wherein said metal layer includes tantalum, tungsten, titanium, cobalt or nickel.

5. The method of claim 1, wherein a top portion of said trapezoidal region has a width that is greater than or equal to a channel length of said transistor.

6. The method of claim 5, wherein said channel length is less than or equal to approximately 0.07 μ

m and said silicide contact includes cobalt silicide.

7. The method of claim 6, wherein said top portion has as width that is at least 0.10 μ

m.

8. An integrated circuit including a field effect transistor having a salicided gate element structure, wherein said transistor includes a polysilicon gate element formed between a pair of vertical spacers defining a gate trench, said polysilicon gate element having a generally trapezoidal shaped region formed over said gate trench and at least partially overlapping said spacers, said trapezoidal shaped region having a silicide contact formed therein.

9. The integrated circuit of claim 8, wherein said silicide contact region is substantially free from silicide agglomeration.

10. The integrated circuit of claim 9, wherein said silicide contact region includes a titanium, tungsten, cobalt, tantalum or nickel silicide.

11. The integrated circuit of claim 9, wherein a top portion of said trapezoidal region has a width that is greater than or equal to a channel length of said transistor.

12. The integrated circuit of claim 11, wherein said channel length is less than or equal to approximately 0.07 μ

m and said silicide contact includes cobalt silicide.

13. The integrated circuit of claim 12, wherein said top portion width is greater than or equal to 0.10 μ

m.

14. The integrated circuit If claim 13, wherein a base portion of said trapezoidal region overlaps each of said spacers between about 0.02-0.05 μ

m.

15. A method of forming a low resistance salicided gate structure of a field effect transistor, comprising the following steps:

etching an insulating layer deposited over a substrate to define a gate trench region of said transistor, said gate trench region having a gate dielectric layer formed therein;

depositing a blanket layer of polysilicon over said insulating layer and within said gate trench region;

planarizing said blanket layer of polysilicon;

etching said planarized layer of polysilicon and said insulating layer to form a generally T-shaped polysilicon gate element and a pair of vertical spacers including a portion of said insulating layer, said generally T-shaped polysilicon gate element at least partially overlapping said spacers; and

forming a silicide contact in said T-shaped polysilicon gate element.

16. The method of claim 15, wherein said silicide formation step includes the step of depositing a refractory metal layer over said polysilicon gate element and processing said metal layer to form said silicide contact.

17. The method of claim 16, wherein a top portion of said polysilicon gate element is sized to substantially prevent silicide agglomeration in said silicide contact.

19. The method of claim 15, wherein said transistor has a channel length that is less than or equal to approximately 0.07 μ

m and said silicide contact includes cobalt silicide.

20. The method of claim 19, wherein said top portion has a width that is greater than or equal to 0.10 μ

m.

21. The method of claim 20, wherein said top portion only partially overlaps said vertical spacers.

22. The method of claim 21, wherein said top portion overlaps each of said vertical spacers between about 0.02-0.05 μ

m.

18. The method of claim 18, wherein said metal layer includes tantalum, tungsten, titanium, cobalt or nickel.

23. A method of forming a low resistance salicided gate structure of a field effect transistor, comprising the following steps:

forming a pair of vertical spacers over a substrate, said spacers defining a gate trench region having a gate dielectric layer formed therein;

depositing a blanket layer of polysilicon over said spacers and in said gate trench region;

planarizing said deposited layer of polysilicon;

selectively etching said planarized polysilicon layer to form a polysilicon gate element having a generally trapezoidal shaped polysilicon region over said gate trench, wherein a base of said trapezoidal region at least partially overlaps each of said spacers; and

depositing a layer of cobalt over said trapezoidal region and processing said cobalt layer to form a cobalt silicide contact in said trapezoidal region,

wherein said trapezoidal region is sized to substantially prevent silicide agglomeration in said cobalt silicide contact.

24. The method of claim 23, wherein a top portion of said trapezoidal region has a width that is greater than or equal to a channel length of said transistor.

25. The method of claim 24, wherein said channel length is less that or equal to approximately 0.07 μ

m, and a top portion and said base of said trapezoidal region have respective widths that are greater than at least 0.10 μ

m.

26. A method of forming a low resistance salicided gate structure of a field effect transistor, comprising the following steps:

etching an insulating layer deposited over a substrate to define a gate trench region of said transistor, said gate trench region having a gate dielectric layer formed therein;

depositing a blanket layer of polysilicon over said insulating layer and within said gate trench region;

planarizing a top surface of said blanket layer of polysilicon;

etching said planarized layer of polysilicon and said insulating layer to form a generally T-shaped polysilicon gate element and a pair of vertical spacers including a remaining portion of said insulating layer, said T-shaped polysilicon gate element at least partially overlapping each of said spacers; and

depositing a layer of cobalt over said polysilicon gate element and processing said cobalt layer to form a cobalt silicide contact in a top portion of said polysilicon gate element,

wherein said top portion is sized to substantially prevent silicide agglomeration in said cobalt silicide contact.

27. The method of claim 26, wherein said transistor has a channel length that is less than or equal to approximately 0.07 μ

m and said top portion has a width that is greater than or equal to 0.10 μ

m.

28. The method of claim 27, wherein said top portion only partially overlaps said vertical spacers.

29. The method of claim 28, wherein said top portion overlaps each of said vertical spacers between about 0.02-0.05 μ

m.