Method for production of contacts on a wafer

• US 20040142548A1
• Filed: 12/18/2003
• Published: 07/22/2004
• Est. Priority Date: 12/18/2002
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Haffner, Henning, Graf, Werner, Heineck, Lars, Kowalewski, Johannes
• Granted Patent: US 7,094,674 B2
• Time in Patent Office: Days
• US Class Current: 438/597
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

The invention relates to a method for production of contacts on a wafer, preferably with the aid of a lithographic process. The preferred embodiment provides a method which overcomes the disadvantages of the complex point/hole lithography process, and which avoids any increase in the process complexity. This method is achieved in that a strip structure extending over two layers is used to structure the contacts. The strip structure in the first layer is rotated at a predetermined angle with respect to the strip structure in the second layer, and the contacts are formed in the mutually overlapping areas of the strip structures in the two layers.

Claims

1. A method of forming a semiconductor device, the method comprising:

providing a surface that includes a plurality of contacts laid out in a matrix of rows and columns;

forming a first plurality of strips over the surface, each strip in the first plurality contacting ones of the contacts disposed along a diagonal of the matrix;

forming a second plurality of strips over the surface and over the first plurality of strips, each strip in the second plurality disposed along a row of the matrix; and

removing portions of the first plurality of strips not underlying the second plurality of strips.

2. The method of claim 1 wherein the first plurality of strips is formed by means of a lithographic process using a first exposure mask and wherein the second plurality of strips is formed by means of a lithographic process using a second exposure mask.

3. The method of claim 2 wherein the lithographic process uses a positive resist.

4. The method of claim 1 wherein the first plurality of strips comprises a plurality of parallel strips and wherein the second plurality of strips comprises a plurality of parallel strips.

5. The method of claim 1 wherein the angle between the first plurality of strips and the second plurality of strips is about 45 degrees.

6. The method of claim 1 wherein the strips in the second plurality of strips are corrugated.

7. The method of claim 1 wherein strips in the first plurality of strips have a different pitch than strips in the second plurality of strips.

8. The method of claim 6 wherein strips in the first plurality of strips have a width that is the same as a width of strips in the second plurality of strips and wherein a distance between strips in the first plurality of strips is different than a distance between strips in the second plurality of strips.

9. The method of claim 7 wherein the distance between strips in the first plurality of strips is greater than the distance between strips in the second plurality of strips.

10. The method of claim 1 wherein removing portions comprises over-etching a space between the strips in the second plurality of strips.

11. The method of claim 9 wherein the semiconductor device comprises a memory array and wherein the contacts comprise memory cell contacts, and wherein the strips in the second plurality of strips line along a row line for memory cells.

12. The method of claim 10 wherein the second plurality of strips is formed in an MO metallization.

13. A method for producing contacts on a wafer, wherein the method comprises a lithographic process in which a strip structure extending over two layers is used for the structuring of the contacts, wherein the method is characterized in that the strip structure in the first layer is rotated at a predetermined angle with respect to the strip structure in the second layer, and the contacts are formed in mutually overlapping areas of the strip structures in the two layers.

14. The method of claim 13 wherein the strip structures are formed by means of a lithographic process, using a first and a second exposure mask, wherein each exposure mask has a parallel strip structure.

15. The method of claim 14 wherein the predetermined angle is a 45 degree angle.

16. The method of claim 14 wherein the strip structures are corrugated in selected areas of a layer.

17. The method of claim 14 wherein the strip structures are provided with corrections in selected areas of a layer.

18. The method of claim 14 wherein the parallel strip structure in one layer has a greater distance between one strip center and an adjacent strip center than the distance between one strip center and an adjacent strip center of another strip structure of another layer.

19. The method of claim 18 wherein a width of the strips in one strip structure is the same as a width of the strips in another strip structure and wherein a space between the strips of one strip structure is greater than a space between the strips of another strip structure.

20. The method of claim 19 wherein the rotated strip structure has the greater space between the strips.

21. The method of claim 13 wherein forming the contacts comprises over-etching a space between the strip structures in the second layer.

22. The method of claim 21 wherein the strip structure in the second layer is formed in an M0 metallization layer and the strip structure in the first layer is formed in a CB (bitline contact) layer.

23. The method of claim 22 wherein the M0 metallization layer forms a row line for memory cells arranged in a same row.