Floating point bypass register to resolve data dependencies in pipelined instruction sequences

• US 20040143613A1
• Filed: 01/07/2004
• Published: 07/22/2004
• Est. Priority Date: 01/07/2003
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Clemen, Rainer, Mielich, Harald, Haess, Jergen, Gerwig, Guenter, Sigal, Leon Jacob, Schwarz, Eric Mark, Fleischer, Bruce Martin
• Application Number:
  US10/752,957
• Publication Number:
  US 20040143613A1
• Time in Patent Office: Days
• US Class Current: 708/233
• CPC Class Codes: G06F 2207/3884 Pipelining
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00

Abstract

A floating point unit of an in-order-processor having a register array for storing a plurality of operands, a pipeline for executing floating point instructions with a plurality of stages, each stage having a stage register, data input registers (1A, 1B, 1C) for keeping operands to be processed. The data input registers form the first stage register of the pipeline. An input port loads operands from outside said floating point unit into one of said data input registers. A plurality of bypass-registers are provided, the input of which is connected to the input port, and the output of which is provided to the data input registers (1A, 1B, 1C), such that data propagating through the pipeline to be loaded into the register array can be immediately supplied to one or more particular data input registers (1A, 1B, 1C) from a respective bypass-register without a delay caused by additional pipeline stages to be propagated through.

Claims