Optoelectronic devices having arrays of quantum-dot compound semiconductor superlattices therein

• US 20040144985A1
• Filed: 01/20/2004
• Published: 07/29/2004
• Est. Priority Date: 06/25/2001
• Status: Active Grant

• Current Assignee: Mehmet Ozturk, Salah M.A. Bedair, Veena Misra, Zhibo Zhang
• Original Assignee: Mehmet Ozturk, Salah M.A. Bedair, Veena Misra, Zhibo Zhang
• Inventors: Misra, Veena, Zhang, Zhibo, Ozturk, Mehmet, Bedair, Salah M. A.
• Granted Patent: US 6,914,256 B2
• Time in Patent Office: Days
• US Class Current: 257/79
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02642 Mask materials other than SiO2 or SiN
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/125 Quantum wire structures
• CPC Class Codes: H01L 29/127 Quantum box structures
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less

Abstract

Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm. The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer.

Claims

1. An opto-electronic device, comprising:

a substrate comprising a first III-V semiconductor layer;

an electrically insulating layer that extends on the first III-V semiconductor layer and comprises an array of non-photolithographically defined nanopores therein;

an array of vertical quantum-dot superlattices in the array of nanopores; and

a second III-V semiconductor layer on said array of vertical quantum-dot superlattices.

2. The device of claim 1, wherein the nanopores in the array have an average diameter in a range between about 8nm and about 50 nm.

3. The device of claim 1, wherein the first III-V semiconductor layer is an N-type semiconductor layer;

and wherein the second III-V semiconductor layer is a P-type semiconductor layer.

4. The device of claim 1, wherein the first III-V semiconductor layer is an N-type Al_xGa_1-xAs layer;

and wherein the second III-V semiconductor layer is a P-type Al_xGa_1-xAs layer.

5. The device of claim 1, wherein the first III-V semiconductor layer comprises an N-type GaAs layer and an N-type Al_xGa_1-xAs layer on the N-type GaAs layer.

6. The device of claim 5, wherein said electrically insulating layer comprises an anodized aluminum oxide layer having the array of non-photolithographically defined nanopores therein.

7. The device of claim 6, wherein each of a plurality of vertical quantum-dot superlattices in the array of nanopores comprises an alternating arrangement of InGaAs and GaAs dots therein.

8. The device of claim 7, wherein said second III-V semiconductor layer comprises a P-type Al_xGa_1-xAs layer that contacts said electrically insulating layer and a P-type GaAs layer that extends on the P-type Al_xGa_1-xAs layer.

9. The device of claim 5, wherein said electrically insulating layer comprises a silicon dioxide layer having the array of non-photolithographically defined nanopores therein.

10. The device of claim 9, wherein each of a plurality of vertical quantum-dot superlattices in the array of nanopores comprises an alternating arrangement of InGaAs and GaAs dots therein.

11. The device of claim 10, wherein said second III-V semiconductor layer comprises a P-type Al_xGa_1-xAs layer that contacts said electrically insulating layer and a P-type GaAs layer that extends on the P-type Al_xGa_1-xAs layer.

12. An opto-electronic device, comprising:

an electrically insulating layer having an array of non-photolithographically defined nanopores therein; and

an array of vertical quantum-dot compound semiconductor superlattices in the array of nanopores.

13. The device of claim 12, wherein said electrically insulating layer comprises an anodized aluminum oxide layer.

14. The device of claim 12, wherein said electrically insulating layer comprises a silicon dioxide layer.

15. The device of claim 13, wherein each of a plurality of vertical quantum-dot superlattices in the array of nanopores comprises an alternating arrangement of InGaAs and GaAs dots therein.

16. The device of claim 12, wherein each of a plurality of vertical quantum-dot superlattices in the array of nanopores comprises an alternating arrangement of InGaAs and GaAs dots therein.