Reconfigurable analog-to-digital converter

• US 20040145508A1
• Filed: 01/12/2004
• Published: 07/29/2004
• Est. Priority Date: 12/12/2000
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Lee, Hae-Seung, Gulati, Kush
• Granted Patent: US 6,864,822 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: H03M 1/005 among different converters types
• CPC Class Codes: H03M 1/007 among different resolutions
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/442 using switched capacitors
• CPC Class Codes: H03M 3/398 among different converter types
• CPC Class Codes: H03M 3/458 Analogue/digital converters using delta-sigma modulation as an intermediate step

Abstract

A reconfigurable ADC includes a plurality of reconfigurable blocks for allowing the ADC to provide a plurality of architectures. In one embodiment, the ADC can be configured to operate in a pipeline mode and a sigma-delta mode. This arrangement provides an ADC having a relatively large range of bandwidth and resolution.

Claims

1. An ADC circuit, comprising:

a plurality of blocks that can be configured to provide a selected one of plurality of analog-to-digital architectures.

2. The circuit according to claim 1, wherein the plurality of analog-to-digital architectures includes a pipeline architecture and a sigma-delta architecture.

3. The circuit according to claim 1, wherein the plurality of analog-to-digital architectures includes at least two architectures selected from the group consisting of pipeline, sigma-delta, and cyclic.

4. The circuit according to claim 1, wherein selected ones of the blocks can be configured for sigma-delta and for pipeline architectures.

5. The circuit according to claim 2, wherein the ADC is configured to the sigma-delta architecture for a desired resolution above a predetermined number of bits.

6. The circuit according to claim 1, wherein at least one of the plurality of blocks includes a capacitor array, a switch matrix and an opamp.

7. The circuit according to claim 6, wherein a bias current level supplied to the opamp corresponds to an input clock frequency.

8. The circuit according to claim 7, further including a phase-locked loop circuit having a voltage controlled oscillator for determining the bias current level.

9. The circuit according to claim 8, wherein the voltage controlled oscillator includes at least one opamp that is substantially similar to the op amp in the at least one block.

10. The circuit according to claim 8, wherein an oscillation frequency of the voltage controlled oscillator is proportional to a speed of the opamp in the at least one block.

11. The circuit according to claim 1, wherein selected ones of the plurality of blocks include capacitors having scaled capacitance values to provide parametric reconfigurability.

12. The circuit according to claim 2, wherein the sigma-delta architecture includes a fourth order distributed feedback cascade of integrators configuration.

13. The circuit according to claim 12, wherein an oversampling rate for the sigma-delta architecture corresponds to a selected resolution.

14. The circuit according to claim 12, wherein the sigma-delta architecture is provided by a selected four of the plurality of blocks.

15. The circuit according to claim 2, wherein a predetermined number of the plurality of blocks is configured for the pipeline architecture based upon a resolution of the ADC.

16. The circuit according to claim 1, wherein the ADC has a resolution ranging from about two bits to about eighteen bits.

17. The circuit according to claim 1, wherein the ADC has a bandwidth ranging from about 1 Hz to about 20 MHz.

18. The circuit according to claim 1, further including a global chopping circuit for canceling opamp offsets.

19. The circuit according to claim 1, further including a 1.5 bit/stage digital correction circuit.

20. The circuit according to claim 1, wherein the circuit is reconfigurable in at least two modes selected from the group consisting of architecture, bandwidth and parametric.

21. A reconfigurable ADC circuit, comprising:

a plurality of cascaded reconfigurable circuit blocks, each of the plurality of reconfigurable circuit blocks including a capacitor array, at least one switch matrix, and an opamp, wherein the reconfigurable blocks can be configured to provide a selected one of a plurality of ADC architectures.

22. The circuit according to claim 21, wherein the plurality of ADC configurations is selected from the group consisting of pipeline and sigma-delta.

23. The circuit according to claim 21, further including a phase-locked loop circuit for receiving an input clock signal and providing bias currents to the opamps in each of the reconfigurable blocks, wherein the bias currents are linearly proportional to input clock frequency.

24. The circuit according to claim 22, wherein the phase-locked loop circuit further includes a voltage controlled oscillator.

25. The circuit according to claim 21, wherein the ADC circuit is reconfigurable architecturally, parametrically and in bandwidth.

26. A method of converting an analog signal to a digital signal, comprising:

configuring a plurality of blocks to a selected one of at least two architectures.

27. The method according to claim 26, wherein the at least two architectures include pipeline.

28. The method according to claim 26, wherein at least two architectures include sigma-delta.

29. The method according to claim 26, further including providing bias currents to opamps in each of the plurality of blocks such that the bias currents are linearly proportional to an input clock frequency.

30. The method according to claim 26, further including selecting a bandwidth for the ADC.

31. The method according to claim 26, further including selecting a parameter for the ADC including resolution.