Reconfigurable logic device

• US 20040145942A1
• Filed: 11/13/2003
• Published: 07/29/2004
• Est. Priority Date: 05/16/2001
• Status: Active Grant

• Current Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Leijten-Nowak, Katarzyna
• Granted Patent: US 7,251,672 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G06F 1/03 working, at least partly, by table look-up G06F1/025 takes precedence
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

A reconfigurable logic device according to the invention comprises a lookup table (LUT) (11.1) with an input (in1) for receiving an input signal and an output (out) for providing a binary output signal. The reconfigurable logic device is characterized by, a control input (ctrl) for receiving a control signal, a controllable inverting gate (11.2) for providing the address signal to the LUT (11.1) in response to the control signal and the input signal, and by a controllable inverting gate (11.3) for providing a modified output signal in response to the output signal of the LUT and the control signal.

The reconfigurable logic device according to the invention can operate at a high speed, and at the same time have a relatively modest configuration memory.

Claims

1. Reconfigurable logic device comprising a logic element with a lookup table (LUT) (11.1), an input (in1) for receiving an input signal and an output (out) for providing an output signal,

characterized by,

a control input (ctrl) for receiving a control signal,

a controllable inverting gate (11.2) for providing an address signal to the LUT (11.1) in response to the control signal (ctrl) and the input signal (in1),

a controllable inverting gate (11.3) for providing a modified output signal (out′

) in response to the output signal of the LUT (11.3) and the control signal.

2. Reconfigurable logic device according to claim 1, characterized by one or more further inputs (in2) for receiving input signals.

3. Reconfigurable logic device according to claim 2, characterized in that one or more additional inputs (in, in2, in3) are coupled to the LUT (12.1) via a a controllable inverting gate (12.3, 12.4, 12.5, 12.6) which provides an address signal to the LUT (12.1) in response to the control signal and the address signal received at said additional inputs (in1, in2, in3).

4. Reconfigurable logic device according to claim 1, characterized in that the LUT (12.2) has one or more additional outputs (O2) which are coupled to an EXOR-gate (12.8) for providing a modified output signal in response to the output signal at said output of the LUT (12.2) and the control signal.

5. Reconfigurable logic device according to claim 1, characterized in that the carry output signal for an n-bit addition is generated in an independent circuit (14.5).

6. Reconfigurable logic device according to claim 1, characterized in that the LUT (12.1, 12.2) is implemented as a multi-output LUT.

7. Reconfigurable logic device according to claim 3, characterized by a multiplexer (12.9) which is controlled by a selection signal (SL) so as to select from at least a first and a second modified output signal as the output signal of the logic element.

8. Multiplication array comprising a plurality of multiplication elements (16.i.j) formed by a reconfigurable logic device according to one of the previous claims, which multiplication elements (16.i.j) further comprise an AND-unit (18.1) with at least one AND-gate for calculating the product of an input bit (ai) of a first number (a) and an input bit (bj) of a second number (b), wherein the reconfigurable logic device (18.2,18.3,18.4) calculates the sum (PPi.j) of this product (ai.bj) and an input partial product (PPi−

1.j+1).

9. Multiplication array according to the previous claim characterized in that at least two multiplication elements (16.1.0 and 16.2.0) are combined in a reconfigurable logic device which calculates an n+1 bit number (c_out|PPi+1.j|PPi.j) as the sum of a n bit number (PPi.j+1|PPi−

1.j+1), the bits of which are partial products obtained by predecessor multiplication elements, an n bit number (ai+1.bj|ai.bj) obtained by multiplying n bits of the first input signal with an input bit of the second signal and a one bit carry in signal (c_in).