High resolution digital pulse width modulator for DC-DC voltage converter

• US 20040146101A1
• Filed: 01/24/2003
• Published: 07/29/2004
• Est. Priority Date: 01/24/2003
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Pearce, Lawrence G.
• Granted Patent: US 7,206,343 B2
• Time in Patent Office: Days
• US Class Current: 375/238
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

A digitally-implemented pulse width modulation (PWM) signal generator forms the PWM pulse width as a rational number based on full cycles of a PWM reference clock, and offers a very high effective resolution of the PWM pulse signal that is compatible with multiphase DC-DC converters. Being totally digital allows digital error accumulation and correction to occur at the point of origin of the PWM signal, well upstream of the relatively slow voltage control feedback loop. Quantization errors are corrected before they can accumulate in the converter'"'"'s DC output voltage.

Claims

1. A method comprising the steps of:

(a) generating a plurality of digital code words, each of which has a most significant bits portion and a least significant bits portion;

(b) generating a plurality of pulse width modulation (PWM) signals having prescribed time parameters respective thereof respectively defined in accordance with most significant bits portions of said digital code words; and

(c) iteratively adjusting said prescribed time parameters of said PWM signals in accordance with least significant bits portions of said digital code words.

2. The method according to claim 1, wherein step (c) further comprises selectively adjusting switching times of said PWM signals.

3. The method according to claim 1, wherein step (c) comprises adjusting a prescribed time parameter of one PWM signal in accordance with the least significant bits portion of a digital code word used to generate another PWM signal.

4. The method according to claim 1, wherein step (c) comprises adjusting a prescribed time parameter of a PWM signal in accordance with the least significant bits portion of a digital code word used to generate a previously generated PWM signal.

5. The method according to claim 1, wherein step (a) comprises generating respective sequences of digital code words, each of which has a most significant bits portion and a least significant bits portion, step (b) comprises generating associated sequences of pulse width modulation (PWM) signals having prescribed time parameters thereof respectively defined in accordance with most significant bits portions of said respective sequences of digital code words, and step (c) comprises iteratively adjusting prescribed time parameters of PWM signals of a first of said respective sequences of PWM signals, in accordance with least significant bits portions of digital code words associated with PWM signals of a second of said respective sequences of PWM signals.

6. The method according to claim 5, wherein step (c) comprises iteratively adjusting prescribed time parameters of PWM signals of a given sequence of PWM signals in accordance with least significant bits portions of digital code words associated with PWM signals of a previously generated sequence of PWM signals.

7. The method according to claim 1, wherein step (a) comprises generating respective sequences of digital code words associated with respectively different phases of PWM signals, each of which has a most significant bits portion and a least significant bits portion, step (b) comprises generating associated sequences of pulse width modulation (PWM) signals for said respectively different phases having respective prescribed time parameters thereof respectively defined in accordance with most significant bits portions of said respective sequences of digital code words, and step (c) comprises iteratively adjusting prescribed time parameters of PWM signals of a first of said respectively different phases in accordance with least significant bits portions of digital code words associated with PWM signals of a second of said respectively different phases.

8. The method according to claim 1, wherein

a respective one of said PWM signals has a switching period comprised of a number D₀ of system clock cycles, and a control loop command duty-cycle η

_n for the n^th pulse,

the corrected n^th pulse duty-cycle h_n is defined as;

$h_n={\mathrm{\eta <br><br>}}_n-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Gamma <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\varepsilon <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Gamma <br><br>}}$

where Γ

may be selected to be either 1 or the number of independent PWM signal channels (phases),

the pulse width P_n, in system clock cycles, for the n^th period is defined as;

P_n=round(D₀h_n),

and

the n^th period duty-cycle error ε

_n is defined as;

ε

_n=P_n/D₀−

η

_n

9. The method according to claim 1, wherein a respective one of said PWM signals has an initial frequency with a period equal to a number D₀ of system clock cycles, the initial period error δ

₀ of which is set to zero,

the initial duty-cycle error ε

₀ is set at zero,

the control loop command duty-cycle is η

_n for the n^th pulse,

the n^th pulse switching cycle target value is defined as;

$D_n^{*}=D_0-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Phi <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\delta <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Phi <br><br>}}$

where Φ

is the number of phases,

the n^th pulse corrected duty-cycle h_n is defined as;

$h_n={\mathrm{\eta <br><br>}}_n-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Gamma <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\varepsilon <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Gamma <br><br>}}$

where Γ

may be selected to be either 1 or the number of independent PWM signal channels (phases),

the pulse width P_n, in system clock cycles, for the n^th period is defined as;

P_n=round(D*_nh_n),

the final period length for the n^th pulse is defined as;

D_n=round(P_n/h_n),

the n^th pulse duty-cycle error is defined as;

ε

_n=P_n/D_n−

η

_n,

and

the n^th period length error δ

_n is defined as;

δ

_n=D_n−

D₀.

10. The method according to claim 1, wherein

a respective one of said PWM signals has a switching period comprised of a number D₀ of system clock cycles, and a control loop command duty-cycle η

_n for the n^th pulse,

the corrected n^th pulse duty-cycle h_n is defined as;

$h_n={\mathrm{\eta <br><br>}}_n-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Gamma <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\varepsilon <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Gamma <br><br>}}$

where Γ

may be selected to be either 1 or the number of independent PWM signal channels (phases),

the pulse width P_n, in system clock cycles, for the n^th period is defined as;

P_n=floor(D₀h_n),

and

the n^th period duty-cycle error ε

_n is defined as;

ε

_n=P_n/D₀−

η

_n

11. The method according to claim 1, wherein a respective one of said PWM signals has an initial frequency with a period equal to a number D₀ of system clock cycles, the initial period error ε

₀ of which is set to zero,

the initial duty-cycle error ε

₀ is set at zero,

the control loop command duty-cycle is η

_n for the n^th pulse,

the n^th pulse switching cycle target value is defined as;

$D_n^{*}=D_0-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Phi <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\delta <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Phi <br><br>}}$

where Φ

is the number of phases,

the n^th pulse corrected duty-cycle h_n is defined as;

$h_n={\mathrm{\eta <br><br>}}_n-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Gamma <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\varepsilon <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Gamma <br><br>}}$

where Γ

may be selected to be either 1 or the number of independent PWM signal channels (phases),

the pulse width P_n, in system clock cycles, for the n^th period is defined as;

P_n=floor(D*_nh_n),

the final period length for the n^th pulse is defined as;

D_n=floor(P_n/h_n),

the n^th pulse duty-cycle error is defined as;

ε

_n=P_n/D_n−

η

_n,

and

the n^th period length error δ

_n is defined as;

δ

_n=D_n−

D₀.

12. The method according to claim 1, wherein

a respective one of said PWM signals has a switching period comprised of a number D₀ of system clock cycles, and a control loop command duty-cycle η

_n for the n^th pulse,

the corrected n^th pulse duty-cycle h_n is defined as;

$h_n={\mathrm{\eta <br><br>}}_n-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Gamma <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\varepsilon <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Gamma <br><br>}}$

where Γ

may be selected to be either 1 or the number of independent PWM signal channels (phases),

the pulse width P_n, in system clock cycles, for the n^th period is defined as;

P_n=ceiling(D₀h_n),

and

the n^th period duty-cycle error ε

_n is defined as;

ε

_n=P_n/D₀−

η

_n

13. The method according to claim 1, wherein a respective one of said PWM signals has an initial frequency with a period equal to a number D₀ of system clock cycles, the initial period error ε

₀ of which is set to zero,

the initial duty-cycle error so is set at zero,

the control loop command duty-cycle is η

_n for the n^th pulse,

the n^th pulse switching cycle target value is defined as;

$D_n^{*}=D_0-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Phi <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\delta <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Phi <br><br>}}$

where Φ

is the number of phases,

the n_th pulse corrected duty-cycle h_n is defined as;

$h_n={\mathrm{\eta <br><br>}}_n-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Gamma <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\varepsilon <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Gamma <br><br>}}$

where Γ

may be selected to be either 1 or the number of independent PWM signal channels (phases),

the pulse width P_n, in system clock cycles, for the n^th period is defined as;

P_n=ceiling(D*_nh_n)

the final period length for the n^th pulse is defined as;

D_n=ceiling(P_n/h_n),

the n^th pulse duty-cycle error is defined as;

ε

_n=P_n/D_n−

η

_n,

and

the n^th period length error δ

_n is defined as;

δ

_n=D_n−

D₀.

14. The method according to claim 1, further including the step of:

(d) controlling a DC-DC converter in accordance with said PWM signals, said DC-DC converter being coupled to receive a supply voltage, and being operative to generate a regulated DC output voltage derived from said supply voltage, said DC-DC converter including a switching circuit containing electronic power switching devices coupled between respective power supply terminals, and controllably switched in accordance with said PWM signals, and having a common node thereof coupled to an output voltage terminal providing said regulated output voltage.

15. The method according to claim 14, wherein step (c) further comprises selectively adjusting switching times of said PWM signals.

16. The method according to claim 15, wherein step (c) comprises selectively adjusting prescribed time parameters and switching times of said PWM signals as necessary to effectively maintain a variation of a prescribed time parameter within a prescribed error tolerance over plural PWM signals.

17. The method according to claim 15, wherein step (c) comprises selectively adjusting prescribed time parameters and switching times of said PWM signals as necessary to effectively produce a zero time average of the digital PWM quantization error of a prescribed time parameter over plural PWM signals.

18. The method according to claim 17, wherein step (a) comprises generating respective sequences of digital code words associated with respectively different phases of PWM signals, each of which has a most significant bits portion and a least significant bits portion, step (b) comprises generating associated sequences of pulse width modulation (PWM) signals for said respectively different phases having prescribed time parameters thereof respectively defined in accordance with most significant bits portions of said respective sequences of digital code words, and step (c) comprises adjusting prescribed time parameters of PWM signals of a respective one of said different phases in accordance with least significant bits portions of digital code words associated with previous PWM signals of said respective one of said different phases.

19. The method according to claim 18, further including the step of:

(d) controlling a DC-DC converter in accordance with said PWM signals, said DC-DC converter being coupled to receive a supply voltage, and being operative to generate a regulated output voltage derived from said supply voltage, said DC-DC converter including a switching circuit containing electronic power switching devices, that are coupled between respective power supply terminals, and are controllably switched in accordance with said PWM signals, and having a common node thereof coupled to an output voltage terminal providing said regulated output voltage.

20. The method according to claim 1, wherein

a respective one of said PWM signals has a fixed switching period comprised of a fixed number D₀ of system clock cycles, and a control loop command duty-cycle η

_n for the n^th pulse,

the corrected n^th pulse duty-cycle h_n is defined as;

$h_n={\mathrm{\eta <br><br>}}_n-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Gamma <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\varepsilon <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Gamma <br><br>}}$

where Γ

=1,

the pulse width P_n, in system clock cycles, for the n^th period is defined as;

P_n=round(D₀h_n),

and

the n^th period duty-cycle error ε

_n is defined as;

ε

_n=P_n/D₀−

η

_n

21. The method according to claim 1, wherein

a respective one of said PWM signals has a variable switching period comprised of a variable number of system clock cycles.

22. The method according to claim 1, wherein a respective one of said PWM signals has an initial frequency with a period equal to a number D₀ of system clock cycles, the initial period error δ

₀ of which is set to zero,

the initial duty-cycle error ε

₀ is set at zero,

the control loop command duty-cycle is η

_n for the n^th pulse,

the n^th pulse switching cycle target value is defined as;

$D_n^{*}=D_0-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Phi <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\delta <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Phi <br><br>}}$

where Φ

is the number of phases,

the n^th pulse corrected duty-cycle h_n is defined as;

$h_n={\mathrm{\eta <br><br>}}_n-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Gamma <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\varepsilon <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Gamma <br><br>}}$

where Γ

=1,

the pulse width P_n, in system clock cycles, for the n^th period is defined as;

P_n=round(D*_nh_n),

the final period length for the n^th pulse is defined as;

D_n=round(P_n/h_n),

the n^th pulse duty-cycle error is defined as;

ε

_n=P_n/D_n−

η

_n

and

the n^th period length error δ

_n is defined as;

δ

_n=D_n−

D₀.

23. The method according to claim 1, wherein

a respective one of said PWM signals has a fixed switching period comprised of a fixed, number D₀ of system clock cycles, and a control loop command duty-cycle η

_n for the n^th pulse,

the corrected n^th pulse duty-cycle h_n is defined as;

$h_n={\mathrm{\eta <br><br>}}_n-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Gamma <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\varepsilon <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Gamma <br><br>}}$

where Γ

corresponds to the number of independent plural PWM signal channels (phases),

the pulse width P_n, in system clock cycles, for the n^th period is defined as;

P_n=round(D₀h_n),

and

the n^th period duty-cycle error ε

_n is defined as;

ε

_n=P_n/D₀−

η

_n

24. The method according to claim 1, wherein a respective one of said PWM signals has an initial frequency with a period equal to a number D₀ of system clock cycles, the initial period error δ

₀ of which is set to zero,

the initial duty-cycle error ε

₀ is set at zero,

the control loop command duty-cycle is η

_n for the n^th pulse,

the n^th pulse switching cycle target value is defined as;

$D_n^{*}=D_0-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Phi <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\delta <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Phi <br><br>}}$

where Φ

is the number of phases,

the n^th pulse corrected duty-cycle h_n is defined as;

$h_n={\mathrm{\eta <br><br>}}_n-\underset{k=1}{\overset{\lfloor <br><br>\frac{n}{\mathrm{\Gamma <br><br>}}\rfloor <br><br>}{\sum <br><br>}}<br><br>{\mathrm{\varepsilon <br><br>}}_{n-k<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{\Gamma <br><br>}}$

where Γ

corresponds to the number of independent plural PWM signal channels (phases),

the pulse width P_n, in system clock cycles, for the n^th period is defined as;

P_n=round(D*_nh_n)

the final period length for the n^th pulse is defined as;

D_n=round(P_n/h_n),

the n^th pulse duty-cycle error is defined as;

ε

_n=P_n/D_n−

η

_n,

and

the n^th period length error δ

_n is defined as;

δ

_n=D_n−

D₀.

25. A method according to claim 1, wherein said prescribed parameter corresponds to duty cycle.

26. A method of generating a regulated direct current (DC) output voltage comprising the steps of:

(a) coupling a supply voltage to a DC-DC converter that is operative to generate a regulated output voltage derived from said supply voltage, said DC-DC converter having a pulse width modulation (PWM) generator which generates a PWM switching signal that switchably controls operation of a switching circuit containing electronic power switching devices coupled between respective power supply terminals, a common node thereof being coupled to an output voltage terminal; and

(b) controlling the operation of said PWM generator by

(b1) generating a plurality of digital code words, each of which has a most significant bits portion and a least significant bits portion,

(b2) generating a plurality of pulse width modulation (PWM) signals having prescribed time parameters duty-cycles thereof respectively defined in accordance with most significant bits portions of said digital code words, and

(b3) iteratively adjusting said prescribed time parameters of said PWM signals in accordance with least significant bits portions of said digital code words.

27. The method according to claim 26, wherein step (b1) comprises generating said plurality of digital code words in accordance with said supply voltage.

28. The method according to claim 26, wherein said prescribed parameter corresponds to duty cycle.

29. An apparatus for generating a regulated direct current (DC) output voltage comprising:

a DC-DC converter that is operative to generate a regulated output voltage derived from said supply voltage, said DC-DC converter including a pulse width modulation (PWM) generator which generates a PWM switching signal that switchably controls operation of a switching circuit containing electronic power switching devices coupled between respective power supply terminals, a common node thereof being coupled to an output voltage terminal; and

a controller which is operative to control the operation of said PWM generator by generating a plurality of digital code words, each of which has a most significant bits portion and a least significant bits portion, generating a plurality of pulse width modulation (PWM) signals having prescribed time parameters thereof respectively defined in accordance with most significant bits portions of said digital code words, and iteratively adjusting the said prescribed time parameters of said PWM signals in accordance with least significant bits portions of said digital code words.

30. The apparatus according to claim 29, wherein said controller is operative to selectively adjust duty and switching cycles of said PWM signals as necessary to effectively maintain a variation of said duty-cycles within a prescribed error tolerance over plural PWM signals.

31. The apparatus according to claim 29, wherein said controller is operative to adjust the duty-cycle of one PWM signal in accordance with the least significant bits portion of a digital code word used to generate another PWM signal.

32. The apparatus according to claim 29, wherein said prescribed time parameter corresponds to duty cycle.