ALGORITHM OF BIT SYNCHRONIZATION FOR A DIGITAL FSK CORRELATION RECEIVER

• US 20040146125A1
• Filed: 01/27/2003
• Published: 07/29/2004
• Est. Priority Date: 01/27/2003
• Status: Active Grant

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: CHEN, YUNG-LUNG, SHIUNG, DAVID
• Granted Patent: US 7,269,233 B2
• Time in Patent Office: Days
• US Class Current: 375/334
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

An algorithm for bit synchronization in a frequency shift keying (FSK) receiver. In the algorithm, a training sequence is received from a transmitter. The training sequence has a plurality of bits. A starting point of a next bit received by the FSK receiver after the training sequence is determined according to peak values of the bits of the training sequence.

Claims

1. An algorithm for bit synchronization in a frequency shift keying (FSK) receiver, the algorithm comprising:

receiving a training sequence from a transmitter, wherein the training sequence having a plurality of bits;

determining peak values corresponding to each of the received bits in a corresponding test range of each of the received bits; and

determining a starting point of a next bit received by the FSK receiver after the training sequence in according to the peak values.

2. The algorithm of claim 1, the each of the bits being divided into a plurality of points, the peak value being determined according to the points of the bit in the corresponding test range.

3. The algorithm of claim 2, wherein the peak value is a maxima value in the in the corresponding test range if the bit is “

1”

.

4. The algorithm of claim 2, wherein the peak value is a minima value in the corresponding test range if the bit being “

1”

.

5. The algorithm of claim 1, wherein the start point of the next bit received by the FSK receiver is determined by summing the peak values, dividing the summation by the number of the bits, and then adding a bias value.

6. The algorithm of claim 5, wherein the bias value is predetermined and set according to the length of the training sequence.

7. The algorithm of claim 5, wherein the bias value is determined and set by summing the number of points of all of the bits in the training sequence, and dividing the summation by the number of the bits.

8. A frequency shift keying (FSK) receiver using the algorithm for bit synchronization as claimed in claim 1

9. An algorithm for bit synchronization in a frequency shift keying (FSK) receiver, the algorithm comprising:

receiving a training sequence from a transmitter, wherein the training sequence having a plurality of bits; and

determining a starting point of a next bit received by the FSK receiver after the training sequence according to peak values of the bits of the training sequence.

10. The algorithm of claim 9, the each of the bits being divided into a plurality of points, the peak value being determined according to the points of the bit in the corresponding test range.

11. The algorithm of claim 10, wherein the peak value is a maxima value in the in the corresponding test range if the bit is “

1” and

the peak value is a minima value in the corresponding test range if the bit being “

0”

.

12. The algorithm of claim 9, wherein the start point of the next bit received by the FSK receiver is determined by summing the peak values, dividing the summation by the number of the bits, and then adding a bias value.

13. The algorithm of claim 12, wherein the bias value is predetermined and set according to the length of the training sequence.

14. The algorithm of claim 12, wherein the bias value is determined and set by summing the number of points of all of the bits in the training sequence, and dividing the summation by the number of the bits.

15. A frequency shift keying (FSK) receiver using the algorithm for bit synchronization as claimed in claim 9.