Methods and apparatus for forming rhodium-containing layers

• US 20040147086A1
• Filed: 01/09/2004
• Published: 07/29/2004
• Est. Priority Date: 08/26/1998
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Uhlenbrock, Stefan, Marsh, Eugene P.
• Granted Patent: US 7,226,861 B2
• Time in Patent Office: Days
• US Class Current: 438/396
• CPC Class Codes: C23C 16/16 from metal carbonyl compounds
• CPC Class Codes: C23C 16/18 from metallo-organic compounds
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/7687 Thin films associated with contacts of capacitors
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/312 with a bit line higher than the capacitor

Abstract

A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula L_yRhY_z is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.

Claims

1. A capacitor, comprising a first conductive layer, a dielectric layer, and a second conductive layer, at least one of said first and second conductive layers containing a CVD platinum-rhodium alloy.

2. The capacitor of claim 1 wherein said dielectric layer is selected from the group consisting of tantalum pentoxide (Ta₂O₅), Barium Strontium Titanate (BST), Strontium Titanate (ST), Lead Zirconium Titanate (PZT), Strontium Bismuth Tantalate (SBT) and Bismuth Zirconium Titanate (BZT).

3. The capacitor of claim 1 wherein said at least one CVD platinum-rhodium alloy conductive layer comprises a bottom electrode for said capacitor.

4. The capacitor of claim 1 wherein said dielectric layer comprises Ta₂O₅.

5. The capacitor of claim 1 wherein said capacitor is a container capacitor.

6. A capacitor, comprising a dielectric layer, a first conductive layer, a second conductive layer, and a conductive barrier layer containing a CVD platinum-rhodium alloy.

7. The capacitor of claim 6, wherein said dielectric layer is selected from the group consisting of tantalum pentoxide (Ta₂O₅), Barium Strontium Titanate (BST), Strontium Titanate (ST), Lead Zirconium Titanate (PZT), Strontium Bismuth Tantalate (SBT) and Bismuth Zirconium Titanate (BZT).

8. The capacitor of claim 6 wherein said first conductive layer comprises an electrode for said capacitor and is interposed between said dielectric and said barrier layer.

9. The capacitor of claim 6 wherein said first conductive layer comprises an electrode for said capacitor and said barrier layer is interposed between said dielectric and said first conductive layer.

10. The capacitor of claim 6 wherein said dielectric layer comprises Ta₂O₅.

11. The capacitor of claim 6 wherein said capacitor comprises a container capacitor.

12. An integrated circuit comprising a capacitor, said capacitor comprising a first conductive layer, a dielectric layer, and a second conductive layer, at least one of said first and second conductive layers containing a CVD platinum-rhodium alloy.

13. The integrated circuit of claim 12 wherein said dielectric layer is selected from the group consisting of tantalum pentoxide (Ta₂O₅), Barium Strontium Titanate (BST), Strontium Titanate (ST), Lead Zirconium Titanate (PZT), Strontium Bismuth Tantalate (SBT) and Bismuth Zirconium Titanate (BZT).

14. The integrated circuit of claim 12 wherein said at least one conductive layer is a bottom electrode for said capacitor.

15. The integrated circuit of claim 12 wherein said dielectric layer comprises Ta₂O₅.

16. The integrated circuit of claim 12 wherein said capacitor is a container capacitor.

17. An integrated circuit comprising a capacitor, said capacitor comprising a dielectric layer, a first conductive layer, a second conductive layer, and a conductive barrier layer, said barrier layer containing a CVD platinum-rhodium alloy.

18. The integrated circuit of claim 17, wherein the capacitor is a container capacitor.

19. The integrated circuit of claim 17, wherein the circuit is a memory circuit.

20. The integrated circuit of claim 19, wherein the circuit is a dynamic random access memory circuit.

21. A memory cell comprising:

a transistor; and

a capacitor having a dielectric diffusion barrier layer containing a CVD platinum-rhodium alloy.

22. The memory cell of claim 21, wherein said capacitor further comprises a dielectric layer selected from the group consisting of tantalum pentoxide (Ta₂O₅), Strontium Titanate (ST), Barium Strontium Titanate (BST), Lead Zirconium Titanate (PZT), Strontium Bismuth Titanate (SBT) and Bismuth Zirconium Titanate (BZT).

23. A method for fabricating a capacitor comprising the steps of:

forming a first conductive layer;

forming a dielectric layer atop said first conductive layer;

forming a second conductive layer atop said dielectric layer;

wherein at least one of said first and second conductive layers contains a CVD platinum-rhodium alloy.

24. The method of claim 23 wherein said first conductive layer is interposed between said barrier layer and said dielectric.

25. The method of claim 23 wherein said second conductive layer is interposed between said barrier and said dielectric.

26. The method of claim 23 wherein said dielectric is selected from the group consisting of tantalum pentoxide (Ta₂O₅), Strontium Titanate (ST), Barium Strontium Titanate (BST), Lead Zirconium Titanate (PZT), Strontium Bismuth Tantalate (SBT) and Bismuth Zirconium Titanate (BZT).

27. The method of claim 23 wherein said conductive barrier layer is formed by chemical vapor co-deposition of platinum and rhodium precursor compositions.

28. The method of claim 27 wherein said platinum precursor composition comprises MeCpPt (Me)₃, where Me is a methyl group and Cp is cyclopentadienyl.

29. The method of claim 27 wherein said rhodium precursor composition comprises CpRh(CO)₂, where Cp is cyclopentadienyl.

30. The method of claim 27 wherein said chemical vapor co-deposition is conducted in a reaction chamber at a temperature in the range of about 100 to about 600°

C.

31. The method of claim 27 wherein said chemical vapor co-deposition is conducted in a reaction chamber at a temperature in the range of about 200 to about 50°

C.

32. The method of claim 27 wherein said chemical vapor co-deposition is conducted in a reaction chamber at a pressure in the range of about 0.1 torr to about 10 torr.

33. The method of claim 27 wherein said chemical vapor co-deposition is conducted by depositing a ratio of rhodium to platinum in the range of about 0.5 to about 99.5% rhodium.

34. The method of claim 27 wherein said chemical vapor co-deposition is conducted by depositing a ratio of rhodium to platinum in the range of about 2% to about 10% rhodium.

35. The method of claim 27 wherein said chemical vapor co-deposition is conducted by depositing a ratio of rhodium to platinum of about 5%.

36. The method of claim 27 wherein said vapor co-deposition is conducted using a reacting gas comprising a gas selected from the group consisting of organic peroxides, O₂, O₃, NO, N₂O, SO₃, H₂, NH₃, and H₂O₂.

37. A method for fabricating a capacitor comprising the steps of:

forming a first conductive layer;

forming a dielectric layer atop said first conductive layer;

forming a second conductive layer atop said dielectric layer; and

forming a conductive barrier layer containing a platinum-rhodium alloy.

38. The method of claim 37 wherein said first conductive layer is interposed between said barrier layer and said dielectric.

39. The method of claim 37 wherein said second conductive layer is interposed between said barrier and said dielectric.

40. The method of claim 37 wherein said dielectric is selected from the group consisting of tantalum pentoxide (Ta₂O₅), Strontium Titanate (ST), Barium Strontium Titanate (BST), Lead Zirconium Titanate (PZT), Strontium Bismuth Tantalate (SBT) and Bismuth Zirconium Titanate (BZT).

41. The method of claim 37 wherein said conductive barrier layer is formed by chemical vapor co-deposition of platinum and rhodium precursor compositions.

42. The method of claim 41 wherein said platinum precursor composition comprises MeCpPt (Me)₃, where Me is a methyl group and Cp is cyclopentadienyl.

43. The method of claim 41 wherein said rhodium precursor composition is selected from the group consisting of CpRh(CO)₂ and MeCpRh(CO)₂, where Cp is cyclopentadienyl.

44. The method of claim 41 wherein said chemical vapor co-deposition is conducted in a reaction chamber at a temperature in the range of about 100 to about 600°

C.

45. The method of claim 41 wherein said chemical vapor co-deposition is conducted in a reaction chamber at a temperature in the range of about 200 to about 500°

C.

46. The method of claim 41 wherein said chemical vapor co-deposition is conducted in a reaction chamber at a pressure in the range of about 0.1 torr to about 10 torr.

47. The method of claim 41 wherein said chemical vapor co-deposition is conducted by depositing a ratio of rhodium to platinum in the range of about 0.5 to about 99.5% rhodium.

48. The method of claim 41 wherein said chemical vapor co-deposition is conducted by depositing a ratio of rhodium to platinum in the range of about 2% to about 10% rhodium

49. The method of claim 41 wherein said chemical vapor co-deposition is conducted by depositing a ratio of rhodium to platinum of about 5%.

50. The method of claim 41 wherein said vapor co-deposition is conducted using a reacting gas comprising a gas selected from the group consisting of organic peroxides, O₂, O₃, NO, N₂O, SO₃, NH₃, H₂ and H₂O₂.

51. A method for fabricating a capacitor having a first and a second electrode, comprising the following steps:

forming an insulative layer overlying a substrate;

forming an opening in said insulative layer in order to expose said substrate;

forming a conductive plug in said opening, said conductive plug forming a first portion of the first electrode of said capacitor, said conductive plug recessed below a surface of said insulative layer;

forming a first conductive layer, for preventing diffusion of atoms, in said opening and overlying said conductive plug such that said first conductive layer is surrounded on sidewalls by said insulative layer, said first conductive layer forming a second portion of the first electrode, said first conductive layer being formed of a platinum-rhodium alloy co-deposited by chemical vapor deposition; and

forming a second conductive layer overlying said first conductive layer, said second conductive layer forming a third portion of the first electrode.

52. The method of claim 51, further comprising the steps of:

creating a dielectric layer to overly said second conductive layer, said first conductive layer substantially preventing oxidation of said dielectric layer; and

creating the second electrode overlying said dielectric layer, said first and the second electrode and said dielectric layer forming the capacitor.

53. The method of claim 52, wherein said step of forming the second electrode comprises sputtering an electrically conductive material to overly said dielectric layer.

54. The method of claim 51, wherein said step of forming said first conductive layer comprises the following steps:

admitting a platinum precursor composition to a chemical vapor deposition reaction chamber;

admitting a rhodium precursor composition to said chemical vapor deposition reaction chamber; and

applying sufficient reaction gas to said chemical vapor deposition reaction chamber to cause co-deposition of a platinum-rhodium alloy.

55. The method of claim 52, wherein said step of forming said dielectric layer comprises depositing a dielectric material from a group of materials consisting of tantalum pentoxide (Ta₂O₅), Barium Strontium Titanate (BST), Strontium Titanate (ST), Lead Zirconium Titanate (PZT), Strontium Bismuth Tantalate (SBT) and Bismuth Zirconium Titanate (BZT).

56. The method of claim 51, further comprising the step of planarizing said insulative layer prior to forming said conductive plug.

57. The method of claim 51, wherein said step of forming said conductive plug comprises depositing in-situ doped polysilicon in said opening.

58. The method of claim 52, wherein the step of forming said second conductive layer comprises forming said second conductive layer with a material selected from a group consisting of refractory metals, noble metals, conductive metal oxides, and metal nitrides.

59. The method of claim 58, wherein said step of forming said dielectric layer comprises depositing a dielectric material from a group of materials consisting of tantalum pentoxide (Ta₂O₅), Barium Strontium Titanate (BST), Strontium Titanate (ST), Lead Zirconium Titanate (PZT), Strontium Bismuth Tantalate (SBT) and Bismuth Zirconium Titanate (BZT).

60. A method of manufacturing a semiconductor structure, the method comprising:

providing a semiconductor substrate or substrate assembly;

providing a precursor composition comprising one or more complexes of the formula;

L_yRhY_z,

wherein;

each L group is independently a neutral or anionic ligand;

each Y group is independently a pi bonding ligand selected from the group of CO, NO, CN, CS, N₂, PX₃, PR₃, P(OR)₃, AsX₃, AsR₃, As(OR)₃, SbX₃, SbR₃, Sb(OR)₃, N_xR_3-x, CNR, and RCN, wherein R is an organic group, X is a halide, and x=0 to 3;

y=1 to 4; and

z=0 to 4;

providing a nonhydrogen reaction gas; and

forming a rhodium-containing layer from the precursor composition in the presence of the nonhydrogen reaction gas on a surface of the semiconductor substrate or substrate assembly.

61. The method of claim 60 wherein the step of forming a rhodium-containing layer comprises vaporizing the precursor composition and directing it toward the semiconductor substrate or substrate assembly using a chemical vapor deposition technique.

62. The method of claim 61 wherein the chemical vapor deposition technique comprises flash vaporization, bubbling, microdroplet formation, or combinations thereof.

63. The method of claim 60 wherein the semiconductor substrate comprises a silicon wafer or a gallium arsenide wafer.

64. The method of claim 60 wherein each R group is a C₁-C₈ organic group.

65. The method of claim 60 wherein the precursor composition is a liquid.

66. The method of claim 65 wherein the liquid precursor composition comprises a solid dissolved in a solvent.

67. The method of claim 60 wherein the precursor composition is vaporized in the presence of an inert carrier gas.

68. The method of claim 60 wherein the nonhydrogen reaction gas is an oxidizing gas selected from the group of organic peroxides, O₂, O₃, SO₃, H₂O, H₂O₂, nitrogen oxides, RuO₄, and combinations thereof.

69. The method of claim 60 wherein the nonhydrogen reaction gas is a reducing gas selected from the group of NH₃, N₂H₄, and combinations thereof.

70. The method of claim 60 wherein the nonhydrogen reaction gas is selected from the group of SiH₄, Si₂H₆, H₂S, H₂Se, H₂Te, and combinations thereof.

71. The method of claim 60 wherein the rhodium-containing layer is a single transition metal or alloy layer.

72. The method of claim 60 wherein z=1 to 4.

73. A method of manufacturing a semiconductor structure, the method comprising:

providing a semiconductor substrate or substrate assembly;

providing a precursor composition comprising one or more organic solvents and one or more complexes of the formula;

L_yRhY_z,

wherein;

each L group is independently a neutral or anionic ligand;

each Y group is independently a pi bonding ligand selected from the group of CO, NO, CN, CS, N₂, PX₃, PR₃, P(OR)₃, AsX₃, AsR₃, As(OR)₃, SbX₃, SbR₃, Sb(OR)₃, NH_xR_3-x, CNR, and RCN, wherein R is an organic group, X is a halide, and x=0 to 3;

y=1 to 4;

z=0 to 4; and

providing a nonhydrogen reaction gas; and

vaporizing the precursor composition to form vaporized precursor composition; and

directing the vaporized precursor composition toward the semiconductor substrate or substrate assembly to form a rhodium-containing layer in the presence of the nonhydrogen reaction gas on a surface of the semiconductor substrate or substrate assembly.

74. A method of forming a layer on a substrate, the method comprising:

providing a substrate;

providing a precursor composition comprising one or more complexes of the formula;

L_yRhY_z,

wherein;

each L group is independently a neutral or anionic ligand;

each Y group is independently a pi bonding ligand selected from the group of CO, NO, CN, CS, N₂, PX₃, PR₃, P(OR)₃, AsX₃, AsR₃, As(OR)₃, SbX₃, SbR₃, Sb(OR)₃, NH_xR_3-x, CNR, and RCN, wherein R is an organic group, X is a halide, and x=0 to 3;

y=1 to 4; and

z=0 to 4;

providing a nonhydrogen reaction gas; and

forming a rhodium-containing layer from the precursor composition in the presence of the nonhydrogen reaction gas on a surface of the substrate.

75. The method of claim 74 wherein the step of forming a rhodium-containing layer comprises vaporizing the precursor composition and directing it toward the substrate using a chemical vapor deposition technique.

76. The method of claim 75 wherein the precursor composition is a liquid.

77. A method of forming a layer on a substrate, the method comprising:

providing a substrate;

providing a precursor composition comprising one or more solvents and one or more complexes of the formula;

L_yRhY_Z,

wherein;

each L group is independently a neutral or anionic ligand;

each Y group is independently a pi bonding ligand selected from the group of CO, NO, CN, CS, N₂, PX₃, PR₃, P(OR)₃, AsX₃, AsR₃, As(OR)₃, SbX₃, SbR₃, Sb(OR)₃, NH_xR_3-x, CNR, and RCN, wherein R is an organic group, X is a halide, and x=0 to 3;

y=1 to 4; and

z=0 to 4;

providing a nonhydrogen reaction gas; and

vaporizing the precursor composition to form vaporized precursor composition; and

directing the vaporized precursor composition toward the substrate to form a rhodium-containing layer in the presence of the nonhydrogen reaction gas on a surface of the substrate.

78. A method of forming a layer on a substrate, the method comprising:

providing a substrate;

providing a precursor composition comprising one or more complexes of the formula;

L_yRhY_z,

wherein;

each L group is independently a neutral or anionic ligand;

each Y group is independently a pi bonding ligand selected from the group of CO, NO, CN, CS, N₂, PX₃, PR₃, P(OR)₃, AsX₃, AsR₃, As(OR)₃, SbX₃, SbR₃, Sb(OR)₃, NH_xR_3-x, CNR, and RCN, wherein R is an organic group, X is a halide, and x=0 to 3;

with the proviso that L is not cyclopentadienyl when Y is CO;

y=1 to 4; and

z=1 to 4; and

forming a rhodium-containing layer from the precursor composition on a surface of the substrate.

79. A method of manufacturing a semiconductor structure, the method comprising:

providing a semiconductor substrate or substrate assembly;

providing a precursor composition comprising one or more complexes of the formula;

L_yRhY_z,

wherein;

each L group is independently a neutral or anionic ligand;

each Y group is independently a pi bonding ligand selected from the group of CO, NO, CN, CS, N₂, PX₃, PR₃, P(OR)₃, AsX₃, AsR₃, As(OR)₃, SbX₃, SbR₃, Sb(OR)₃, NH_xR_3-x, CNR, and RCN, wherein R is an organic group, X is a halide, and x=0 to 3;

with the proviso that L is not cyclopentadienyl when Y is CO;

y=1 to 4; and

z=1 to 4; and

forming a rhodium-containing layer from the precursor composition on a surface of the semiconductor substrate or substrate assembly.

80. A chemical vapor deposition apparatus comprising:

a deposition chamber having a substrate positioned therein;

a vessel containing a precursor composition comprising one or more complexes of the formula;

L_yRhY_z,

wherein;

each L group is independently a neutral or anionic ligand;

each Y group is independently a pi bonding ligand selected from the group of CO, NO, CN, CS, N₂, PX₃, PR₃, P(OR)₃, AsX₃, AsR₃, As(OR)₃, SbX₃, SbR₃, Sb(OR)₃, NH_xR_3-x, CNR, and RCN, wherein R is an organic group, X is a halide, and x=0 to 3;

y=1 to 4; and

z=0 to 4;

a source of an inert carrier gas for transferring the precursor composition to the chemical vapor deposition chamber; and

a source of a nonhydrogen reaction gas.