Virtual to physical memory address mapping within a system having a secure domain and a non-secure domain
First Claim
1. Apparatus for processing data, said apparatus comprising:
- a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain or a non-secure domain, said plurality of modes including;
at least one secure mode being a mode in said secure domain; and
at least one non-secure mode being a mode in said non-secure domain;
wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode;
said processor includes a non-secure translation table base address register operable in said non-secure domain to indicate a region of memory storing non-secure domain memory mapping data defining how virtual addresses are translated to physical addresses within said non-secure domain; and
said processor includes a secure translation table base address register operable in said secure domain to indicate a region of memory storing secure domain memory mapping data defining how virtual addresses are translated to physical addresses within said secure domain.
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Accused Products
Abstract
There is provided apparatus for processing data, said apparatus comprising:
a processor operable in a plurality of modes and either a secure domain or a non-secure domain including:
at least one secure mode being a mode in said secure domain; and
at least one non-secure mode being a mode in said non-secure domain;
wherein
when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode;
said processor includes a non-secure translation table base address register operable in said non-secure domain to indicate a region of memory storing non-secure domain memory mapping data defining how virtual addresses are translated to physical addresses within said non-secure domain; and
said processor includes a secure translation table base address register operable in said secure domain to indicate a region of memory storing secure domain memory mapping data defining how virtual addresses are translated to physical addresses within said secure domain.
53 Citations
15 Claims
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1. Apparatus for processing data, said apparatus comprising:
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a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain or a non-secure domain, said plurality of modes including;
at least one secure mode being a mode in said secure domain; and
at least one non-secure mode being a mode in said non-secure domain;
wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode;
said processor includes a non-secure translation table base address register operable in said non-secure domain to indicate a region of memory storing non-secure domain memory mapping data defining how virtual addresses are translated to physical addresses within said non-secure domain; and
said processor includes a secure translation table base address register operable in said secure domain to indicate a region of memory storing secure domain memory mapping data defining how virtual addresses are translated to physical addresses within said secure domain. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of processing data, said method comprising the steps of:
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executing a program with a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain or a non-secure domain, said plurality of modes including;
at least one secure mode being a mode in said secure domain; and
at least one non-secure mode being a mode in said non-secure domain;
wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode;
said processor includes a non-secure translation table base address register operable in said non-secure domain to indicate a region of memory storing non-secure domain memory mapping data defining how virtual addresses are translated to physical addresses within said non-secure domain; and
said processor includes a secure translation table base address register operable in said secure domain to indicate a region of memory storing secure domain memory mapping data defining how virtual addresses are translated to physical addresses within said secure domain. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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Specification