Semiconductor integrated circuit device with connections formed using a conductor embedded in a contact hole
First Claim
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1. A semiconductor integrated circuit device comprising:
- a PMOS transistor formed in a N-type well;
an NMOS transistor formed in a P-type well;
a plurality of contact holes for connecting a first-layer metal line layer with gate electrodes and diffusion layers of said PMOS and NMOS transistors; and
an electrical conductive layer embedded in said plurality of contact holes, wherein said plurality of contact holes have at least two types of plane configurations.
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Accused Products
Abstract
The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.
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Citations
37 Claims
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1. A semiconductor integrated circuit device comprising:
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a PMOS transistor formed in a N-type well;
an NMOS transistor formed in a P-type well;
a plurality of contact holes for connecting a first-layer metal line layer with gate electrodes and diffusion layers of said PMOS and NMOS transistors; and
an electrical conductive layer embedded in said plurality of contact holes, wherein said plurality of contact holes have at least two types of plane configurations. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor integrated circuit device comprising:
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a PMOS transistor formed in a N-type well;
an NMOS transistor formed in a P-type well;
first-layer metal line layers;
second-layer metal line layers;
a plurality of contact holes for connecting said first-layer metal line layers to gate electrodes and diffusion layers of said PMOS and NMOS transistors; and
through holes for connecting said first-layer metal line layers to said second-layer metal line layers, wherein a potential of said N-type well and a potential of said P-type well are controlled independently of each other;
lines for obtaining the potentials of said N-type and P-type wells includes said first-layer metal line layers, electrical conductors formed inside said contact holes, or said electrical conductors formed inside said contact holes and said first-layer metal line layers; and
said second-layer metal line layers wire a power supply potential and a ground potential. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A semiconductor integrated circuit device, comprising:
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a MIS transistor formed in a substrate;
a first line layer formed on said substrate;
a second line layer formed on said first line layer; and
a contact hole for electrically connecting two of a source, gate and drain of said MIS transistor, said first line layer and said second line layer, wherein when an X-Y plane is assumed on a surface of said substrate, configuration of projection onto said X-Y plane of the source, gate and drain of said transistor, said first line layer or said second line layer which are connected by said contact hole has a non-overlapped portion. - View Dependent Claims (16, 17)
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15. A semiconductor integrated circuit device, comprising:
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a MIS transistor formed in a substrate;
a first line layer formed on said substrate;
a second line layer formed on said first line layer; and
a contact hole for electrically connecting two of a source, gate and drain of said MOS transistor, said first line layer and said second line layer, wherein when an X-Y plane is assumed on a surface of said substrate, configuration of projection onto said X-Y plane of a contact portion at which said two of the source, gate and drain of said transistor, said first line layer and said second line layer are connected by said contact hole has a non-overlapped portion.
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18. A semiconductor integrated circuit device, comprising:
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a diffusion layer formed in a substrate;
an intermediate layer formed on said substrate;
a line layer formed on said intermediate layer; and
a contact hole formed within said intermediate layer for electrically connecting said diffusion layer to said line layer, wherein when an X-Y plane is assumed on a surface of said substrate, configuration of projection onto said X-Y plane of a contact portion of said diffusion layer and said contact hole and configuration of projection onto said X-Y plane of a contact portion of said line layer and said contact hole have non-overlapped portions.
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19. A semiconductor integrated circuit device, comprising:
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a first line layer formed on a substrate;
an intermediate layer formed on said first line layer;
a second line layer formed on said intermediate layer; and
a contact hole formed within said intermediate layer for electrically connecting said first line layer to said second line layer, wherein when an X-Y plane is assumed on a surface of said substrate, configuration of projection onto said X-Y plane of a contact portion of said first line layer to said contact hole and configuration of projection onto said X-Y plane of a contact portion of said second line layer and said contact hole have non-overlapped portions. - View Dependent Claims (20, 21)
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22. A semiconductor integrated circuit device, comprising:
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a MIS transistor formed in a substrate;
a first metal line layer formed on said substrate; and
a second metal line layer formed on said first metal line layer, wherein at least a part of a power supply line connected to a source/drain channel in said MIS transistor is constituted by said second metal line layer;
at least a part of a well potential line for controlling a well potential of said MIS transistor is constituted by said first metal line layer; and
at least a part of said power supply line and said well potential line is overlapped. - View Dependent Claims (23, 24, 25, 26, 27)
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28. A semiconductor integrated circuit device, comprising:
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a MIS transistor formed in a substrate;
a first metal line layer formed on said substrate;
an intermediate layer formed between said substrate and said first metal line layer; and
a second metal line layer formed on said first metal line layer, wherein at least a part of a power supply line connected to a source/drain channel in said MIS transistor is constituted by said second metal line layer;
at least a part of a well potential line for controlling a well potential of said MIS transistor is constituted by an electrical conductor which is formed inside a contact hole formed within said intermediate layer; and
said power supply line overlaps with said contact hole. - View Dependent Claims (29)
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30. A semiconductor integrated circuit device, comprising:
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a MIS transistor formed in a substrate;
a first metal line layer formed on said substrate; and
a second metal line layer formed on said first metal line layer, wherein at least a part of a power supply line connected to a source/drain channel in said MOS transistor is constituted by said second metal line layer;
at least a part of a well potential line for controlling a well potential of said MIS transistor is constituted by said first metal line layer; and
said first metal line layer is formed of tungsten as a main constituent; and
said second metal line layer is formed of copper as a main constituent.
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31. A semiconductor integrated circuit device, comprising:
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a MIS transistor formed in a substrate;
a memory cell for storing data;
a first metal line layer formed on said substrate; and
.a second metal line layer formed on said first metal line layer, wherein at least a part of a power supply line connected to a source/drain channel in said MIS transistor is constituted by said second metal line layer;
at least a part of a well potential line for controlling a well potential of said MIS transistor is constituted by said first metal line layer; and
at least a part of a bit line for transmitting an input or output data signal to said memory cell is constituted by said first metal line layer.
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32. A semiconductor integrated circuit device, comprising:
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a MIS transistor formed in a substrate;
a memory cell for storing data;
a first line layer a main constituent of which is tungsten; and
a second line layer a main constituent of which is copper, wherein at least a part of a power supply line connected to a source/drain channel in said MIS transistor is constituted by said second line layer;
at least a part of a well potential line for controlling a well potential of said MIS transistor is constituted by said first line layer; and
at least a part of a bit line for transmitting an input or output data signal to said memory cell is constituted by said first line layer.
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33. A semiconductor integrated circuit device, comprising:
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a MIS transistor formed in a substrate;
a memory cell for storing data;
a first metal line layer formed on said substrate, a main constituent of said first metal line layer being tungsten; and
a second metal line layer formed on said first metal line layer, a main constituent of said second metal line being copper, wherein at least a part of a power supply line connected to a source/drain channel in said MIS transistor is constituted by said second metal line layer; and
at least a part of a bit line for transmitting an input or output data signal to said memory cell is constituted by said first metal line layer. - View Dependent Claims (34, 35, 36, 37)
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Specification