Multilevel interconnect structure with low-k dielectric

• US 20040150109A1
• Filed: 02/02/2004
• Published: 08/05/2004
• Est. Priority Date: 06/13/1997
• Status: Active Grant

• Current Assignee: Kie Y. Ahn, Leonard Forbes
• Original Assignee: Kie Y. Ahn, Leonard Forbes
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Granted Patent: US 7,138,718 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A multilevel interconnect structure with a low-k dielectric constant is fabricated in an integrated circuit structure by the steps of depositing a layer of photoresist on a substrate assembly, etching the photoresist to form openings, forming a metal layer on the photoresist layer to fill the openings and then removing the photoresist layer by, for example, ashing. The metal layer is supported by the metal which filled the openings formed in the photoresist.

Claims

1. A method of fabricating a semiconductor interconnect structure comprising the steps of:

depositing a layer of photoresist on a substrate assembly;

etching the photoresist layer to form a plurality of openings;

depositing a metal layer on the photoresist layer to fill the openings formed in the photoresist layer;

removing the photoresist layer such that the metal layer is supported by the metal which fills the openings formed in the photoresist; and

depositing a low-k dielectric constant film on the interconnect structure.

2. The method of claim 1 wherein the low-k dielectric film is deposited on said metal layer.

3. The method of claim 1 further comprising the step of depositing a bilayer adhesion promoter/diffusion barrier prior to the step of depositing said metal layer.

4. The method of claim 3 wherein said bilayer adhesion promoter/diffusion barrier is deposited by an ionized sputtering process.

5. The method of claim 3 wherein said bilayer adhesion promoter/diffusion barrier is deposited by a chemical vapor depositing process.

6. The method of claim 1 wherein said metal layer comprises a copper containing material deposited by an electroplating process.

7. The method of claim 1 wherein said metal layer comprises a copper containing material deposited by an electroless plating process.

8. The method of claim 1 wherein said metal layer comprises a copper containing material deposited by a chemical vapor depositing process.

9. The method of claim 1 wherein said resist layer is removed by ashing in a plasma.

10. The method of claim 1 wherein said bilayer adhesion promoter/diffusion barrier is selected from the group consisting of titanium/copper, chromium/copper, titanium nitride/copper, tantalum/copper, W/copper and WN/copper.

11. The method of claim 1 wherein said bilayer adhesion promoter/diffusion barrier is selected from the group consisting of W/copper and WN/copper.

12. The method of claim 1 wherein said dielectric film has a dielectric constant of from about 1 to about 2.5.

13. The method of claim 1 wherein said dielectric film has a dielectric constant of from about 1 to about 2.0.

14. The method of claim 1 wherein said dielectric film is selected from the group consisting of aerogels and xerogels.

15. The method of claim 1 wherein the metal layer comprises a copper containing material and has a thickness of from about 0.5 micron to about 1.0 micron.

16. A method of fabricating a multilevel semiconductor interconnect structure comprising the steps of:

(i) depositing a layer of photoresist on a substrate assembly;

(ii) etching the photoresist layer to form a plurality of openings;

(iii) depositing a metal layer on the photoresist layer to fill the openings formed in the photoresist layer;

(iv) repeating the steps of (i) depositing a layer of photoresist, (ii) etching the photoresist layer and (iii) depositing a metal layer until a predetermined number of metal layers levels are formed;

(v) removing the photoresist layers such that the metal layers are supported by the metal which filled the openings formed in the photoresist; and

(vi) depositing a low-k dielectric film on the interconnect structure.

17. The method of claim 16 wherein said resist layers are removed by ashing a plasma into said interconnect structure.

18. The method of claim 16 wherein said bilayer adhesion promoter/diffusion barriers are selected from the group consisting of titanium/copper, chromium/copper, titanium nitride/copper, tantalum/copper, W/copper and WN/copper.

19. The method of claim 16 wherein said bilayer adhesion promoter/diffusion barriers are selected from the group consisting of W/copper and WN/copper.

20. The method of claim 16 wherein said dielectric film has a dielectric constant of from about 1 to about 2.5.

21. The method of claim 16 wherein said dielectric films has a dielectric constant of from about 1 to about 2.0.

22. The method of claim 16 wherein said dielectric film is selected from the group consisting of aerogels and xerogels.

23. The method of claim 16 wherein the metal layers are copper and have a thickness of from about 0.5 micron to about 1.0 micron.

24. A method of claim 16 wherein said metal layers are formed of a copper containing material.

25. A multilevel semiconductor interconnect structure fabricated by the steps comprising:

(i) depositing a layer of photoresist on a substrate assembly;

(ii) etching the photoresist layer to form a plurality of openings;

(iii) depositing a metal layer on the photoresist layer and filling the openings formed in the photoresist layer;

(iv) repeating the steps of (i) depositing a layer of photoresist, (ii) etching the photoresist layer and (iii) depositing a metal layer until a predetermined number of metal layers are formed;

(v) removing the photoresist layers such that the metal layers are supported by the metal which filled the openings formed in the photoresist; and

(vi) depositing a low-k dielectric film on the interconnect structure.

26. The structure of claim 25 further comprising the step of depositing a bilayer adhesion promoter/diffusion barrier on the photoresist layer prior to the step of depositing said metal layer.

27. The structure of claim 26 wherein said bilayer adhesion promoter/diffusion barrier is selected from the group consisting of titanium/copper, chromium/copper, titanium nitride/copper, tantalum/copper, W/copper and WN/copper.

28. The structure of claim 27 wherein said bilayer adhesion promoter/diffusion barrier is selected from the group consisting of W/copper and WN/copper.

29. The structure of claim 25 wherein said dielectric film has a dielectric constant of from about 1 to about 2.5.

30. The structure of claim 25 wherein said dielectric films has a dielectric constant of from about 1 to about 2.0.

31. The structure of claim 25 wherein said dielectric film is selected from the group consisting of aerogels and xerogels.

32. The structure of claim 25 wherein the metal layers are copper and have a thickness of from about 0.5 micron to about 1.0 micron.

33. A semiconductor device comprising:

a substrate assembly; and

at least one interconnect structure on said substrate assembly, said interconnect structure comprising;

a first plurality of metal plugs formed above said substrate assembly;

a metal layer having a portion elevated above said substrate assembly and a portion defining a second plurality of metal plugs formed below said metal layer and in electrical contact with a respective ones of said first plurality of metal plugs such that said metal layer is in electrical contact with the substrate assembly, said plurality of metal plugs supporting said elevated portion of said metal layer;

a gas surrounding said first and second plurality of metal plugs; and

a low-k dielectric film on said metal layer.

34. The semiconductor device of claim 33 wherein said gas is air.

35. A semiconductor device of claim 33 wherein said low-k dielectric film has a dielectric constant of about 1 to about 2.5.

36. A semiconductor device of claim 35 wherein said low-k dielectric film has a dielectric constant of about 1 to 2.0.

37. A semiconductor device of claim 33 wherein said low-k dielectric film comprises one of an aerogel and a xerogel.

38. A semiconductor device of claim 33 wherein said metal plugs and metal layer are formed of a copper containing material.

39. A semiconductor device of claim 33 wherein said metal layer has a thickness of from about 0.5 micron to about 1.0 micron.bstrate, and a diffusion barrier layer of TiN is provided over said metal contacts.

40. A semiconductor device comprising:

a substrate assembly; and

at least one interconnect structure on said substrate assembly, said interconnect structure comprising;

a first bilayer adhesion promoter/diffusion barrier defining a plurality of first receptacles;

a plurality of metal plugs formed in said plurality of first receptacles;

a second bilayer adhesion promoter/diffusion barrier defining a plurality of second receptacles above said metal plugs;

a metal layer having a portion elevated above said substrate assembly and a portion filling said plurality of second receptacles such that said metal layer is in electrical contact with the substrate assembly, said metal filling said second plurality of receptacles and said plurality of metal plugs supporting said elevated portion of said metal layer with a gas surrounding said first and second receptacles; and

a low-k dielectric film on said metal layer.

41. A semiconductor device of claim 40 wherein said gas is air.

42. A semiconductor device of claim 41 wherein said low-k dielectric film has a dielectric constant of about 1 to about 2.5.

43. A semiconductor device of claim 41 wherein said low-k dielectric film has a dielectric constant of about 1 to 2.0.

44. A semiconductor device of claim 43 wherein said low-k dielectric film comprises one of an aerogel and a xerogel.

45. A semiconductor device of claim 41 wherein said metal plugs at metal layer are formed of a copper containing material.

46. A semiconductor device of claim 41 where said metal layer has a thickness of from about 0.5 micron to about 1.0 micron. lower planar metal contacts recessed in said lower insulation substrate, and respective diffusion barrier layers deposited on said lower insulation substrate and said metal contacts.

47. The semiconductor device of claim 41 wherein a diffusion barrier layer of Si₃N₄ is provided over said lower insulation substrate, and a diffusion barrier layer of TiN is provided over said metal contacts.

48. The semiconductor device of claim 41 wherein said bilayer adhesion promoter/diffusion barriers are selected from the group consisting of titanium/copper, chromium/copper, titanium nitride/copper, tantalum/copper, W/copper and WN/copper.

49. The semiconductor device of claim 41 wherein said dielectric film has a dielectric constant of from about 1 to about 2.5.

50. The semiconductor device of claim 41 wherein said dielectric films has a dielectric constant of from about 1 to about 2.0.

51. The semiconductor device of claim 41 wherein said dielectric film is selected from the group consisting of aerogels and xerogels.

52. The semiconductor device of claim 41 wherein the metal layer comprise copper and has a thickness of from about 0.5 micron to about 1.0 micron.

53. The semiconductor device of claim 41 wherein said substrate assembly comprises a lower insulation substrate, a plurality of lower planar metal contacts recessed in said lower insulation substrate, and respective diffusion barrier layers deposited on said lower insulation substrate and said metal contacts.

54. The semiconductor device of claim 53 wherein a diffusion barrier layer of Si₃N₄ is provided over said lower insulation substrate, and a diffusion barrier layer of TiN is provided over said metal contacts.

55. The semiconductor device of claim 41 wherein said first and second bilayer adhesion promoter/diffusion barriers are selected from the group consisting of W/copper and WN/copper.

56. The semiconductor device of claim 41 wherein said dielectric film has a dielectric constant of from about 1 to about 2.5.

57. The semiconductor device of claim 41 wherein said dielectric films has a dielectric constant of from about 1 to about 2.0.

58. The semiconductor device of claim 41 wherein said dielectric film is selected from the group consisting of aerogels and xerogels.

59. The semiconductor device of claim 41 wherein the metal layer comprise copper and has a thickness of from about 0.5 micron to about 1.0 micron.