Low voltage differential signaling driving apparatus

• US 20040150434A1
• Filed: 01/12/2004
• Published: 08/05/2004
• Est. Priority Date: 01/20/2003
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Lu, Chao-Hsin
• Granted Patent: US 7,250,793 B2
• Time in Patent Office: Days
• US Class Current: 327/112
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end

Abstract

A low voltage differential signaling (LVDS) driving apparatus is disclosed, which comprises an LVDS output circuit to output an LVDS differential signal; a switch circuit coupled to the LVDS output circuit to control the phase of the LVDS differential signal; and a reference current control circuit to provide a control voltage to the LVDS output circuit such that the magnitude of the LVDS differential signal is determined based on the control voltage.

Claims

1. A driving apparatus, comprising:

an output circuit to output a differential signal;

a switch circuit coupled to the output circuit to control the phase of the differential signal; and

a reference current control circuit to provide a control voltage to the output circuit such that the magnitude of the differential signal is determined based on the control voltage.

2. The apparatus of claim 1, wherein the output circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor and the second transistor are coupled to a operational voltage source, and the third transistor and the fourth transistor are coupled to the ground.

3. The driving apparatus of claim 2, wherein the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.

4. The driving apparatus of claim 3, wherein the control voltage further includes a first control voltage for controlling the first transistor and the second transistor and a second control voltage for controlling the third transistor and the fourth transistor.

5. The driving apparatus of claim 2, wherein the switch circuit is for selectively turning ON either the first and the fourth transistors or the second and the third transistors, wherein while the first and the fourth transistors are ON, the second and the third transistors are OFF, and while the first and the fourth transistors are OFF, the second and the third transistors are ON.

6. The driving apparatus of claim 5, wherein the switch circuit further comprises:

a first switch to selectively provide a first control voltage signal to the first transistor;

a second switch to selectively provide a second control voltage signal to the third transistor;

a third switch to selectively provide the first control voltage signal to the second transistor; and

a fourth switch to selectively provide the second control voltage signal to the fourth transistor;

a fifth switch to selectively provide a third control voltage signal to the first transistor;

a sixth switch to selectively provide a fourth control voltage signal to the third transistor;

a seventh switch to selectively provide the third control voltage signal to the second transistor; and

an eighth switch to selectively provide the fourth control voltage signal to the fourth transistor;

wherein the first control voltage signal is for turning ON the first and the second transistors, and the second control voltage signal is for turning ON the third and the fourth transistors;

wherein the third control voltage signal is for turning OFF the first and the second transistors, and the fourth control voltage signal is for turning OFF the third and the fourth transistors.

7. The driving apparatus of claim 6, wherein the driving apparatus further includes a switch control circuit to control the operation of the first, the second, the third, the fourth, the fifth, the sixth, the seventh, and the eighth switches.

8. The driving apparatus of claim 6, wherein the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.

9. The driving apparatus of claim 8, wherein the third control voltage signal is provided by the operational voltage source and the fourth control voltage signal is provided by the ground.

10. The driving apparatus of claim 6, wherein the first control voltage signal and the second control voltage signal are provided by the reference current control circuit.

11. The driving apparatus of claim 8, wherein while the second, the third, the fifth, and the eighth transistors are ON, the first, the fourth, the sixth, and the seventh transistors are OFF, and while the second, the third, the fifth, and the eighth transistors are OFF, the first, the fourth, the sixth, and the seventh transistors are ON.

12. The driving apparatus of claim 6, wherein while at least one of the first, the second, the third, the fourth transistors is ON, it operates at a triode region.

13. The driving apparatus of claim 1, wherein the driving apparatus is a low voltage differential signaling (LVDS) driving apparatus.

14. The apparatus of claim 13, wherein the output circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor and the second transistor are coupled to a operational voltage source, and the third transistor and the fourth transistor are coupled to the ground.

15. The driving apparatus of claim 14, wherein the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.

16. The driving apparatus of claim 15, wherein the control voltage further includes a first control voltage for controlling the first transistor and the second transistor and a second control voltage for controlling the third transistor and the fourth transistor.

17. The driving apparatus of claim 14, wherein the switch circuit is for selectively turning ON either the first and the fourth transistors or the second and the third transistors, wherein while the first and the fourth transistors are ON, the second and the third transistors are OFF, and while the first and the fourth transistors are OFF, the second and the third transistors are ON.