Device to receive., buffer, and transmit packets of data in a packet switching network
First Claim
1. A device to create, process and transfer packets of information from one device to another, comprising:
- a plurality of micro-engines to receive payload data from a memory controller, determine if a task is available to process the payload data and assign a task to process the payload data;
a transmit cell FIFO circuit adapted to build a packet header based on payload data received from the plurality of micro-engines or directly from the memory controller and store payload data in a buffer, transmit the packet header with the payload data when all the payload data has been received and immediately begin to receive additional payload data from either the plurality of micro-engines or the memory controller when a predetermined amount of payload data has been transferred out of the buffer.
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Abstract
A device to create, receive, and transmit packets of data in a packet switching network. This device employs a direct memory access packet controller which would interface between memory contained within a computer system and a packet switched network. This direct memory access packet controller would utilize one or more micro-engines that would dynamically allocate buffer space to process received packets of data. This direct memory access packet controller would further utilize a transmit cell FIFO circuit to allocate buffer space to packets being transmitted. In addition, a sequencer would act to control the workflow of packets being received and transmitted.
21 Citations
18 Claims
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1. A device to create, process and transfer packets of information from one device to another, comprising:
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a plurality of micro-engines to receive payload data from a memory controller, determine if a task is available to process the payload data and assign a task to process the payload data;
a transmit cell FIFO circuit adapted to build a packet header based on payload data received from the plurality of micro-engines or directly from the memory controller and store payload data in a buffer, transmit the packet header with the payload data when all the payload data has been received and immediately begin to receive additional payload data from either the plurality of micro-engines or the memory controller when a predetermined amount of payload data has been transferred out of the buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A device to receive packets of information from one device and transfer the packets to another device, comprising:
a plurality of micro-engines to receive a packet from a device, determine if a task is available to process the packet and assign a task and buffer to store the packet, said plurality of micro-engines further comprising;
a dynamic cell buffer circuit adapted to extract a destination work queue from a packet header contained in the packet received from a transmitting device and signal a sequencer that a micro-engine task and dynamic cell buffer are to be assigned for the received packet; and
a cell byte register circuit to extract an opcode for the packet header, determine the number of bytes in the packet header, determine the total number of bytes in the packet payload and determine the number of bytes remaining in the dynamic cell buffer. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A device to create and transmit packets of data, comprising:
a transmit cell FIFO circuit adapted to build a packet header based on payload data received from a plurality of micro-engines or directly from a memory controller, said transmit cell FIFO circuit further comprising;
a buffer control logic circuit adapted to receive packet data from the memory controller or the plurality of micro-engines and place it in a cell buffer FIFO and begin transmitting to a destination when a packet header and payload data have been received; and
a cell buffer byte alignment circuit to track a start lane in the cell buffer FIFO indicating the start of free space in the cell buffer FIFO, to determine a starting lane for alignment of the packet payload matches the start lane for the cell buffer FIFO. - View Dependent Claims (17, 18)
Specification