Fabrication method of so1 semiconductor devices

• US 20040152272A1
• Filed: 03/01/2004
• Published: 08/05/2004
• Est. Priority Date: 03/23/2001
• Status: Abandoned Application

• Current Assignee: Amaury Neve De Mevergnies, Denis Fladre, Jean-Pierre Raskins
• Original Assignee: Amaury Neve De Mevergnies, Denis Fladre, Jean-Pierre Raskins
• Inventors: Raskins, Jean-Pierre, Fladre, Denis, De Mevergnies, Amaury Neve
• Application Number:
  US10/471,847
• Publication Number:
  US 20040152272A1
• Time in Patent Office: Days
• US Class Current: 438/284
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76275 Vertical isolation by bonding techniques
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence

Abstract

The present invention relates to a method for fabrication of semiconductor devices, in particular but not limited to the fabrication of double gate transistors of the type Gate-All-Around or “semiconductor-on-nothing” transistors and devices. A method according to the present invention comprises the steps of: (a) forming a trench in a least a first substrate, (b) transferring semiconductor material over the trench to form a semiconductor bridge across the trench, the semiconductor bridge defining an active area. The bridge may be free to oscillate above the trench without using removing a sacrificial layer. The method may also include the steps of: (c) forming a gate insulator on the semiconductor bridge, and (d) applying gate material on the gate insulator, thus forming a gate.

Claims

1. - A method for fabricating a semiconductor device or circuit, comprising the steps of:

(a) forming a trench (8, 23) in at least a first substrate,

(b) bonding semiconductor material over the trench to form a semiconductor bridge across the trench (8), the bridge having a thickness of 100 nm or less.

2. A method according to claim 1, wherein the semiconductor bridge defined an active area (12), further comprising the steps of:

(c) forming a gate insulator (16) on the semiconductor bridge,

(d) applying conductive gate material (17) onto the gate insulator (16), thus forming a gate.

3. - A method according to claim 1 or 2, wherein the trench is formed in a first semiconductor layer or in a first insulating layer.

4. - A method according to any of the previous claims, wherein the semiconductor material is bonded to cover the whole of the trench.

5. - A method according to claim 4, wherein the semiconductor bridge is formed to cover the whole of the trench.

6. - A method according to any of the claims 1 to 4, wherein the semiconductor bridge is formed to cover a part of the trench.

7. - A method according to claim 6, wherein a cantilever beam is formed from the bridge.

8. - A method according to claim 6, wherein a gate insulator (16) is formed around the semiconductor bridge.

9. - A method according to claim 8, wherein the gate material surrounds the semiconductor bridge with the gate insulator.

10. - A method according to any of claims 2 to 6, wherein the gate insulator is formed on top, bottom and/or sides of the semiconductor bridge.

11. - A method according to claim 10, wherein the gate material is formed on top, bottom and/or sides of the semiconductor bridge, over the gate insulator.

12. - A method according to any of the claims 2 to 10, furthermore comprising the step of:

(e) patterning the gate.

13. - A method according to any of the preceding claims, furthermore comprising the step of:

(f) forming contact regions in the semiconductor bridge.

14. - A method according to claim 13, furthermore comprising the step of:

(g) forming a conductor layer for said contact regions and for said gate.

15. - A method according to claim 6, further comprising forming at least one gate in the bonded semiconductor material, the gate being insulated from the bridge by air.

16. - A method according to claim 15, wherein the gate is formed at the same time as the step of forming the bridge.

17. - A method according to any previous claim, wherein the first substrate comprises a first insulating layer and wherein a supporting wafer comprising a second substrate, a second insulating layer, a second semiconductor layer and a third insulating layer, is bonded with its third insulating layer on the first insulating layer provided with the trench.

18. - A method according to claims 17, wherein the third insulating layer is omitted, and the supporting wafer is bonded with the second semiconductor layer on the first insulating layer provided with the trench.

19. - A method according to any of the claims 1 to 16, wherein the first substrate comprises a first semiconductor layer and wherein a supporting wafer comprising a second substrate, a second insulating layer, a second semiconductor layer and a third insulating layer, is bonded with its third insulating layer on the first semiconductor layer provided with the trench.

20. - A method according to claim 17 or 19, wherein the supporting wafer comprises a second substrate, a cleaving layer, a second semiconductor layer and a third insulating layer or comprises a second substrate and a second semiconductor layer and a third insulating layer with no second insulating layer or cleaving layer.

21. - A method according to any of claims 17 to 20, wherein the second substrate and the second insulating layer are removed after bonding.

22. - A method according to claim 21, wherein the second semiconductor layer of the supporting wafer is patterned to form the semiconductor bridge.

23. - A method according to any of the previous claims, wherein a layer of etch-stop barrier is incorporated into the trench preferably prior to forming the semiconductor bridge.

24. - A method according to any of the previous claims, wherein the trench has dimensions related to the desired size of the semiconductor device fabricated.

25. - A method according to any of the previous claims, wherein alignment marks for subsequent process steps are realised along with the trench.

26. - A method according to any of the previous claims, wherein the trench is structured so that the bottom gate will have a desired shape.