Hexamethyldisilazane treatment of low-k dielectric films

• US 20040152296A1
• Filed: 02/04/2003
• Published: 08/05/2004
• Est. Priority Date: 02/04/2003
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Jin, Changming, Matz, Phillip D., Smith, Patricia B., Park, Heungsoo, McKerrow, Andrew J.
• Application Number:
  US10/357,993
• Publication Number:
  US 20040152296A1
• Time in Patent Office: Days
• US Class Current: 438/623
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas

Abstract

A method of forming an organosilicate low dielectric constant insulating layer (40) in an integrated circuit, and an integrated circuit structure having such a low-k insulating layer (40), are disclosed. In the case where the low-k dielectric material of the insulating layer (40) comprises an organosilicate glass, subsequent plasma processing has been observed to break bonds between silicon and organic moieties, either by replacing an organic group with a hydroxyl group or with hydrogen, or by leaving a dangling bond. Eventually, the damaged insulating layer (40) includes silanol molecules, which results in a degraded film. The disclosed method exposes the damaged insulating layer (40) to a silylation agent such as hexamethyldisilazane, which reacts with the damaged molecules, and forms molecules that restore the properties of the film.

Claims

1. A method of fabricating an integrated circuit at a surface of a substrate, comprising the steps of:

forming active devices at the surface;

depositing an organic low dielectric constant insulating layer over the active devices;

subjecting the insulating layer to a plasma;

after the subjecting step, exposing the insulating layer to a silylation agent; and

after the exposing step, forming a metal conductor near the insulating layer.

2. The method of claim 1, wherein the silylation agent is hexamethyldisilazane.

3. The method of claim 1, wherein the insulating layer comprises an organosilicate glass.

4. The method of claim 1, further comprising:

patterning a masking layer at the surface of the insulating layer, to define locations at which openings are to be etched into the insulating layer; and

etching the insulating layer, using the patterned masking layer as a mask;

wherein the step of subjecting the insulating layer to a plasma comprises;

after the etching step, removing remaining portions of the patterned masking layer using a plasma process.

5. The method of claim 4, wherein the etching step comprises plasma etching the insulating layer.

6. The method of claim 4, wherein the removing step is performed in a plasma chamber;

and wherein the exposing step is performed in the plasma chamber.

7. The method of claim 6, wherein the exposing step is performed in a plasma.

8. The method of claim 4, wherein the removing step is performed in a plasma chamber;

and further comprising;

removing the substrate from the plasma chamber prior to the exposing step.

9. The method of claim 1, wherein the step of subjecting the insulating layer to a plasma comprises:

depositing a cap dielectric layer over the insulating layer.

10. The method of claim 9, further comprising:

after the depositing step, patterning a masking layer at the surface of the insulating layer, to define locations at which openings are to be etched into the insulating layer; and

etching the cap dielectric layer and the insulating layer, using the patterned masking layer as a mask.

11. The method of claim 10, wherein the exposing step is performed prior to the patterning step.

12. The method of claim 11, wherein the step of subjecting the insulating layer to a plasma further comprises:

after the etching step, removing remaining portions of the patterned masking layer using a plasma process;

and further comprising;

after the removing step, again exposing the insulating layer to hexamethyldisilazane.

13. The method of claim 9, further comprising:

after the depositing step, patterning a masking layer at the surface of the insulating layer, to define locations at which openings are to be etched into the insulating layer; and

etching the cap dielectric layer and the insulating layer, using the patterned masking layer as a mask.

wherein the step of subjecting the insulating layer to a plasma further comprises;

after the etching step, removing remaining portions of the patterned masking layer using a plasma process;

and wherein the exposing step is performed after the removing step.

14. The method of claim 2, wherein the exposing step exposes the insulating layer to hexamethyldisilazane in the liquid phase.

15. The method of claim 2, wherein the exposing step exposes the insulating layer to hexamethyldisilazane in the vapor phase.

16. The method of claim 1, further comprising:

patterning a masking layer at the surface of the insulating layer, to define locations at which openings are to be etched into the insulating layer; and

etching the insulating layer, using the patterned masking layer as a mask;

wherein the step of subjecting the insulating layer to a plasma comprises;

after the etching step, removing remaining portions of the patterned masking layer using a plasma process;

and wherein the step of forming a metal conductor comprises depositing a metal into the openings formed in the etching step.

17. The method of claim 16, wherein the metal comprises copper.

18. An integrated circuit, comprising:

active devices disposed near a surface of a substrate;

a first organic low dielectric constant insulating layer disposed over the active devices, and formed according to a process comprising the steps of;

depositing the first insulating layer near the surface;

subjecting the first insulating layer to a plasma; and

after the subjecting step, exposing the first insulating layer to a silylation agent; and

a first metal conductor, disposed near the first insulating layer.

19. The integrated circuit of claim 18, wherein the silylation agent is hexamethyldisilazane.

20. The integrated circuit of claim 18, further comprising:

a second organic low dielectric constant insulating layer disposed over the active devices, over the first insulating layer, and over the first metal conductor, and formed according to a process comprising the steps of;

depositing the second insulating layer;

subjecting the second insulating layer to a plasma; and

after the subjecting step, exposing the second insulating layer to a silylation agent; and

a second metal conductor, disposed near the second insulating layer.

21. The integrated circuit of claim 18, wherein the first insulating layer comprises an organosilicate glass.

22. The integrated circuit of claim 18, wherein the process of forming the first insulating layer further comprises:

patterning a masking layer at the surface of the first insulating layer, to define locations at which openings are to be etched into the first insulating layer; and

etching the first insulating layer, using the patterned masking layer as a mask;

and wherein the step of subjecting the first insulating layer to a plasma comprises;

after the etching step, removing remaining portions of the patterned masking layer using a plasma process.

23. The integrated circuit of claim 18, wherein the step of subjecting the insulating layer to a plasma comprises:

depositing a cap dielectric layer over the first insulating layer.

wherein the etching step also etches the cap dielectric layer;

and wherein the exposing step is performed prior to the patterning step.

24. The integrated circuit of claim 23, wherein the process further comprises:

after the etching step, removing remaining portions of the patterned masking layer using a plasma process; and

after the removing step, again exposing the insulating layer to a silylation agent.

25. A method of fabricating an integrated circuit at a surface of a substrate, comprising the steps of:

forming active devices at the surface;

depositing an organic low dielectric constant insulating layer over the active devices, the insulating layer comprising a material having molecules with silicon-hydrocarbon bonds;

subjecting the insulating layer to a plasma, in which at least some of the silicon-hydrocarbon bonds are broken;

after the subjecting step, exposing the insulating layer to a substance that reacts with molecules in the insulating layer in which the silicon-hydrocarbon bonds were broken in the subjecting step, to form molecules having silicon-hydrocarbon bonds; and

after the exposing step, forming a metal conductor near the insulating layer.

26. The method of claim 25, wherein the insulating layer comprises an organosilicate glass.

27. The method of claim 25, wherein the substance comprises a silylation agent.

28. The method of claim 25, wherein the substance comprises hexamethyldisilazane.