Fencepost descriptor caching mechanism and method therefor
First Claim
1. A method for reducing transfer latencies in fencepost buffering comprising the steps of:
- providing a cache between a network controller and a host entity with shared memory wherein the cache has a top cache and a bottom cache;
fetching a first and second descriptor address location from shared memory wherein the first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a reserve descriptor;
copying the active descriptor to the top cache; and
issuing a command to DMA for transfer of the active descriptor.
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Abstract
A system and method for reducing transfer latencies in fencepost buffering requires that a cache is provided between a host and a network controller having shared memory. The cache is divided into a dual cache having a top cache and a bottom cache. A first and second descriptor address location are fetched from shared memory. The two descriptors are discriminated from one another in that the first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a reserve/lookahead descriptor. The active descriptor is copied to the top cache. A command is issued to DMA for transfer of the active descriptor. The second descriptor address location is then copied into the first descriptor address. The next descriptor address location from external memory is then fetched and placed in the second descriptor address location.
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Citations
17 Claims
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1. A method for reducing transfer latencies in fencepost buffering comprising the steps of:
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providing a cache between a network controller and a host entity with shared memory wherein the cache has a top cache and a bottom cache;
fetching a first and second descriptor address location from shared memory wherein the first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a reserve descriptor;
copying the active descriptor to the top cache; and
issuing a command to DMA for transfer of the active descriptor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for reducing transfer latencies in fencepost buffering having chained descriptors comprising the steps of:
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providing a cache between a host and a network controller having local memory wherein the cache has a top cache and a bottom cache;
fetching a first and second descriptor address location from shared memory wherein the first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a reserve descriptor; and
updating the ownership of terminal descriptors by writing an End of Frame (EOF) descriptor to shared memory before writing a Start of Package (SOP) descriptor to shared memory;
issuing a command to DMA for transfer of the active descriptor. - View Dependent Claims (9, 10, 11, 12)
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13. A system for reducing transfer latencies in fencepost buffering having chained descriptors comprising:
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a network controller;
a host entity with shared memory;
a cache between said network controller and said host entity with shared memory wherein the cache has a top cache and a bottom cache;
means for fetching a first and second descriptor address location from shared memory wherein the first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a reserve descriptor;
means for updating the ownership of terminal descriptors by writing an End of Frame (EOF) descriptor to shared memory before writing a Start of Package (SOP) descriptor to shared memory; and
means for issuing a command to DMA for transfer of the active descriptor. - View Dependent Claims (14, 15, 16, 17)
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Specification