Address scramble

• US 20040153620A1
• Filed: 01/30/2003
• Published: 08/05/2004
• Est. Priority Date: 01/30/2003
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eisen, Shai, Edan, Mori, Varkony, Roni
• Granted Patent: US 6,967,896 B2
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A method for operating a memory cell array, the method comprising assigning word lines of a memory cell array as addresses for writing sets of data thereto from a cache memory, and scrambling addresses of the sets of data by writing a first chunk of the particular set of data from the cache memory to a first word line of the array, and writing a second chunk of the particular set of data from the cache memory to a second word line of the array, the first chunk comprising a first subset of the particular set of data and the second chunk comprising a second subset of the particular set of data.

Claims

1. A method for operating a memory cell array, the method comprising:

assigning word lines of a memory cell array as addresses for writing sets of data thereto from a cache memory; and

scrambling addresses of said sets of data by writing a first chunk of said particular set of data from said cache memory to a first word line of said array, and writing a second chunk of said particular set of data from said cache memory to a second word line of said array, said first chunk comprising a first subset of said particular set of data and said second chunk comprising a second subset of said particular set of data.

2. The method according to claim 1, further comprising reading said particular set of data from said array by serially reading said first chunk from said first word line and reading said second chunk from said second word line.

3. The method according to claim 1, wherein said data comprises at least one byte that comprises at least two chunks of at least four bits.

4. The method according to claim 1, wherein assigning comprises assigning said addresses to bits A1, . . . An in said cache memory, wherein An is the most significant bit (MSB), and assigning A0, the least significant bit (LSB), to a bit of information, called “

chunk select”

, adapted to determine which chunk of said bits is to be read or written.

5. The method according to claim 4, further comprising writing said sets of data to said cache memory while not writing to said chunk select.

6. The method according to claim 1, wherein said first and second word lines comprise adjacent word lines.

7. The method according to claim 1, wherein said first and second word lines comprise non-adjacent word lines.

8. The method according to claim 5, further comprising reading said particular set of data from said array by switching said chunk select from the LSB to bit A1 and assigning the LSB to said first word line, reading said first chunk from said first word line, switching said chunk select from bit A1 to the LSB and assigning bit A1 to said second word line, and reading said second chunk from said second word line.

9. The method according to claim 1, further comprising internally writing from said memory cell array back to said cache memory by descrambling said scrambling of the addresses of said sets of data.