Method and software for partitioned group element selection operation

• US 20040153632A1
• Filed: 01/16/2004
• Published: 08/05/2004
• Est. Priority Date: 08/16/1995
• Status: Active Grant

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Granted Patent: US 8,001,360 B2
• Time in Patent Office: Days
• US Class Current: 712/221
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

Claims

1. A method of processing data in a programmable processor, the method comprising:

decoding a single instruction for selectively arranging data, specifying a data selection operand and a first and a second register each having a register width, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements; and

for each field of the data selection operand, providing the data element selected by the field to a predetermined position in a catenated result.

2. The method of claim 1 wherein each field of the data selection operand provides a sufficient number of bits to specify any one of the plurality of data elements.

3. The method of claim 2 wherein each field of the data selection operand has a width of n bits, wherein the plurality of data elements comprises 2ⁿ data elements.

4. The method of claim 1 wherein the data selection operand is provided by a register specified by the single instruction.

5. The method of claim 4 wherein the data selection operand has a width equal to the specified register width.

6. The method of claim 1 wherein the catenated result is provided to a register.

7. The method of claim 1 wherein the plurality of data elements has a combined width equal to the width of the first register plus the width of the second register.

8. The method of claim 1 wherein the instruction further specifies a data element width of the plurality of data elements.

9. The method of claim 1 wherein each data element has a width of 8 bits.

10. The method of claim 1 wherein the catenated result has a width of 128 bits.

11. The method of claim 1 wherein for each field of the data selection operand, a relative location of the field within the data selection operand corresponds to a relative location of the predetermined position within the catenated result.

12. The method of claim 1 further comprising:

decoding a second single instruction specifying a third and a fourth register each containing a plurality of floating-point operands;

multiplying the plurality of floating point operands in the third register by the plurality of operands in the fourth register to produce a plurality or products; and

providing the plurality of products to partitioned fields of a result register as a catenated result.

13. A method for selectively arranging data in a programmable processor, the method comprising:

decoding a single instruction specifying a data selection operand and a first register having a register width, the first register providing a plurality of data elements each having an elemental width smaller than the register width, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements; and

for each field of the data selection operand, providing the data element selected by the field to a predetermined position in a catenated result.

14. A computer-readable medium:

having instructions that instruct a computer system to perform operations,

at least some of the instructions including a group element selection instruction for selectively arranging data in a programmable processor, the group element selection instruction capable of instructing a computer to perform operations comprising;

decoding the group element selection instruction specifying a data selection operand and a first and a second register each having a register width, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements; and

for each field of the data selection operand, providing the data element selected by the field to a predetermined position in a catenated result.

15. The computer-readable medium of claim 14 wherein each field of the data selection operand provides a sufficient number of bits to specify any one of the plurality of data elements.

16. The computer-readable medium of claim 15 wherein each field of the data selection operand has a width of n bits, wherein the plurality of data elements comprises 2ⁿ data elements.

17. The computer-readable medium of claim 14 wherein the data selection operand is provided by a register specified by the single instruction.

18. The computer-readable medium of claim 17 wherein the data selection operand has a width equal to the specified register width.

19. The computer-readable medium of claim 14 wherein the catenated result is provided to a register.

20. The computer-readable medium of claim 14 wherein the plurality of data elements has a combined width equal to the width of the first register plus the width of the second register.

21. The computer-readable medium of claim 14 wherein the instruction further specifies a data element width of the plurality of data elements.

22. The computer-readable medium of claim 14 wherein each data element has a width of 8 bits.

23. The computer-readable medium of claim 14 wherein the catenated result has a width of 128 bits.

24. The computer-readable medium of claim 14 wherein for each field of the data selection operand, a relative location of the field within the data selection operand corresponds to a relative location of the predetermined position within the catenated result.

25. The computer-readable medium of claim 14 wherein at least some of the instructions further include a group floating point multiply instruction for multiplying floating point data in a programmable processor, the group floating point multiply instruction capable of instructing the computer to perform operations comprising:

decoding the group floating point multiply instruction specifying a third and a fourth register each containing a plurality of floating-point operands;

multiplying the plurality of floating point operands in the third register by the plurality of operands in the fourth register to produce a plurality or products; and

providing the plurality of products to partitioned fields of a result register as a catenated result.

26. A computer-readable medium:

having instructions that instruct a computer system to perform operations,

at least some of the instructions including a group element selection instruction for selectively arranging data in a programmable processor, the group element selection instruction capable of instructing a computer to perform operations comprising;

decoding the group element selection instruction specifying a data selection operand and a first register having a register width, the first register providing a plurality of data elements each having an elemental width smaller than the register width, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements; and

for each field of the data selection operand, providing the data element selected by the field to a predetermined position in a catenated result.

27. A computer data signal, embodied in a transmission medium:

having instructions that instruct a computer system to perform operations,

at least some of the instructions including a group element selection instruction for selectively arranging data in a programmable processor, the group element selection instruction capable of instructing a computer to perform operations comprising;

decoding the group element selection instruction specifying a data selection operand and a first and a second register each having a register width, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements; and

for each field of the data selection operand, providing the data element selected by the field to a predetermined position in a catenated result.

28. The computer data signal of claim 27 wherein each field of the data selection operand provides a sufficient number of bits to specify any one of the plurality of data elements.

29. The computer data signal of claim 28 wherein each field of the data selection operand has a width of n bits, wherein the plurality of data elements comprises 2ⁿ data elements.

30. The computer data signal of claim 27 wherein the data selection operand is provided by a register specified by the single instruction.

31. The computer data signal of claim 30 wherein the data selection operand has a width equal to the specified register width.

32. The computer data signal of claim 27 wherein the catenated result is provided to a register.

33. The computer data signal of claim 27 wherein the plurality of data elements has a combined width equal to the width of the first register plus the width of the second register.

34. The computer data signal of claim 27 wherein the instruction further specifies a data element width of the plurality of data elements.

35. The computer data signal of claim 27 wherein each data element has a width of 8 bits.

36. The computer data signal of claim 27 wherein the catenated result has a width of 128 bits.

37. The computer data signal of claim 27 wherein for each field of the data selection operand, a relative location of the field within the data selection operand corresponds to a relative location of the predetermined position within the catenated result.

38. The computer data signal of claim 27 wherein at least some of the instructions further include a group floating point multiply instruction for multiplying floating point data in a programmable processor, the group floating point multiply instruction capable of instructing the computer to perform operations comprising:

decoding the group floating point multiply instruction specifying a third and a fourth register each containing a plurality of floating-point operands;

multiplying the plurality of floating point operands in the third register by the plurality of operands in the fourth register to produce a plurality or products; and

providing the plurality of products to partitioned fields of a result register as a catenated result.

39. A computer data signal, embodied in a transmission medium:

having instructions that instruct a computer system to perform operations,

at least some of the instructions including a group element selection instruction for selectively arranging data in a programmable processor, the group element selection instruction capable of instructing a computer to perform operations comprising;

decoding the group element selection instruction specifying a data selection operand and a first register having a register width, the first register providing a plurality of data elements each having an elemental width smaller than the register width, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements; and

for each field of the data selection operand, providing the data element selected by the field to a predetermined position in a catenated result.