Hardware driven state save/restore in a data processing system

• US 20040153762A1
• Filed: 10/24/2003
• Published: 08/05/2004
• Est. Priority Date: 11/13/2002
• Status: Abandoned Application

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Flynn, David Walter, Symes, Dominic Hugo
• Application Number:
  US10/691,501
• Publication Number:
  US 20040153762A1
• Time in Patent Office: Days
• US Class Current: 714/15
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream

Abstract

State data from a circuit 2 is saved to a memory 14 via a system bus 4, 6, 8, 10 under control of a state saving controller 16. The state data may be captured within scan chains 12 provided for production test within the circuit with these scan chains supplying respective bits to the multi-bit state saving data words that are stored to the memory via the system bus.

Claims

1. Apparatus for processing data, said apparatus comprising:

a circuit used in processing data, said circuit having one or more nodes operable to store one or more data values that together define a state of said circuit;

a memory operable to store data;

a system bus coupled to said circuit and said memory and operable to transfer multi-bit data words between said circuit and said memory in response to memory transfer requests issued upon said system bus during normal processing operation of said circuit and said memory; and

a state saving controller coupled to said circuit and said system bus and operable in response to a state saving trigger to read said data values defining a state of said circuit from said one or more nodes and to generate a sequence of memory write requests on said system bus that write one or more state saving multi-bit data words representing said data values into said memory such that said state of said circuit is restorable using said one or more state saving multi-bit data words.

2. Apparatus as claimed in claim 1, wherein said circuit is a processor core.

3. Apparatus as claimed in claim 1, wherein said one or more nodes are each coupled to a respective scan chain cell within said circuit, said state saving controller being operable in response to said state saving trigger to store said data values within respective scan chain cells and to serially read said data values from said scan chain cells to form said one or more state saving multi-bit data words.

4. Apparatus as claimed in claim 3, comprising a plurality of scan chains each containing a plurality of scan chain cells, said plurality of scan chains operating in parallel to provide respective bits that together form a state saving multi-bit data word as said plurality of scan chains of serially read.

5. Apparatus as claimed in claim 3, wherein said scan chain cells are also operable to perform test functions upon said circuit.

6. Apparatus as claimed in claim 1, wherein said circuit is a further memory and said data values are bits of data words stored in said further memory.

7. Apparatus as claimed in claim 6, wherein said further memory is coupled to a built-in self-test controller operable to perform self-test operations upon said further memory and said state saving controller uses said built-in self-test controller to read data values from said further memory to form said state saving multi-bit data words.

8. Apparatus as claimed in claim 1, wherein said memory transfers are burst mode memory transfers.

9. Apparatus as claimed in claim 1, wherein said state saving controller is operable in response to a state restoring trigger to generate a sequence of memory read requests on said system bus that read said one or more multi-bit state saving data words from said memory via said system bus and write said data values represented by said multi-bit state saving data words to said one or more nodes to thereby restore said state of said circuit.

10. Apparatus as claimed in claim 1, wherein said multi-bit state saving data words are stored in a user specified region of said memory.

11. Apparatus as claimed in claim 1, wherein said state saving trigger comprises execution of a state saving program instruction.

12. Apparatus as claimed in claim 1, wherein said state saving trigger comprises initiation of a diagnostic test upon said circuit.

13. A method of saving state within an apparatus for data processing having:

a circuit used in processing data, said circuit having one or more nodes operable to store one or more data values that together define a state of said circuit;

a memory operable to store data; and

a system bus coupled to said circuit and said memory and operable to transfer multi-bit data words between said circuit and said memory in response to memory transfer requests issued upon said system bus during normal processing operation of said circuit and said memory;

said method comprising the steps of;

in response to a state saving trigger using a state saving controller coupled to said circuit and said system bus to read said data values defining a state of said circuit from said one or more nodes and to generate a sequence of memory write requests on said system bus that write one or more state saving multi-bit data words representing said data values into said memory such that said state of said circuit is restorable using said one or more state saving multi-bit data words.

14. A method as claimed in claim 13, wherein said circuit is a processor core.

15. A method as claimed in claim 13, wherein said one or more nodes are each coupled to a respective scan chain cell within said circuit, said state saving controller being operable in response to said state saving trigger to store said data values within respective scan chain cells and to serially read said data values from said scan chain cells to form said one or more state saving multi-bit data words.

16. A method as claimed in claim 15, comprising a plurality of scan chains each containing a plurality of scan chain cells, said plurality of scan chains operating in parallel to provide respective bits that together form a state saving multi-bit data word as said plurality of scan chains of serially read.

17. A method as claimed in claim 15, wherein said scan chain cells are also operable to perform test functions upon said circuit.

18. A method as claimed in claim 13, wherein said circuit is a further memory and said data values are bits of data words stored in said further memory.

19. A method as claimed in claim 18, wherein said further memory is coupled to a built-in self-test controller operable to perform self-test operations upon said further memory and said state saving controller uses said built-in self-test controller to read data values from said further memory to form said state saving multi-bit data words.

20. A method as claimed in claim 13, wherein said memory transfers are burst mode memory transfers.

21. A method as claimed in claim 13, wherein said state saving controller is operable in response to a state restoring trigger to generate a sequence of memory read requests on said system bus that read said one or more multi-bit state saving data words from said memory via said system bus and write said data values represented by said multi-bit state saving data words to said one or more nodes to thereby restore said state of said circuit.

22. A method as claimed in claim 13, wherein said multi-bit state saving data words are stored in a user specified region of said memory.

23. A method as claimed in claim 13, wherein said state saving trigger comprises execution of a state saving program instruction.

24. A method as claimed in claim 13, wherein said state saving trigger comprises initiation of a diagnostic test upon said circuit.