Hardware driven state save/restore in a data processing system
First Claim
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1. Apparatus for processing data, said apparatus comprising:
- a circuit used in processing data, said circuit having one or more nodes operable to store one or more data values that together define a state of said circuit;
a memory operable to store data;
a system bus coupled to said circuit and said memory and operable to transfer multi-bit data words between said circuit and said memory in response to memory transfer requests issued upon said system bus during normal processing operation of said circuit and said memory; and
a state saving controller coupled to said circuit and said system bus and operable in response to a state saving trigger to read said data values defining a state of said circuit from said one or more nodes and to generate a sequence of memory write requests on said system bus that write one or more state saving multi-bit data words representing said data values into said memory such that said state of said circuit is restorable using said one or more state saving multi-bit data words.
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Abstract
State data from a circuit 2 is saved to a memory 14 via a system bus 4, 6, 8, 10 under control of a state saving controller 16. The state data may be captured within scan chains 12 provided for production test within the circuit with these scan chains supplying respective bits to the multi-bit state saving data words that are stored to the memory via the system bus.
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Citations
24 Claims
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1. Apparatus for processing data, said apparatus comprising:
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a circuit used in processing data, said circuit having one or more nodes operable to store one or more data values that together define a state of said circuit;
a memory operable to store data;
a system bus coupled to said circuit and said memory and operable to transfer multi-bit data words between said circuit and said memory in response to memory transfer requests issued upon said system bus during normal processing operation of said circuit and said memory; and
a state saving controller coupled to said circuit and said system bus and operable in response to a state saving trigger to read said data values defining a state of said circuit from said one or more nodes and to generate a sequence of memory write requests on said system bus that write one or more state saving multi-bit data words representing said data values into said memory such that said state of said circuit is restorable using said one or more state saving multi-bit data words. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of saving state within an apparatus for data processing having:
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a circuit used in processing data, said circuit having one or more nodes operable to store one or more data values that together define a state of said circuit;
a memory operable to store data; and
a system bus coupled to said circuit and said memory and operable to transfer multi-bit data words between said circuit and said memory in response to memory transfer requests issued upon said system bus during normal processing operation of said circuit and said memory;
said method comprising the steps of;
in response to a state saving trigger using a state saving controller coupled to said circuit and said system bus to read said data values defining a state of said circuit from said one or more nodes and to generate a sequence of memory write requests on said system bus that write one or more state saving multi-bit data words representing said data values into said memory such that said state of said circuit is restorable using said one or more state saving multi-bit data words. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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Specification