Circuit with expected data memory coupled to serial input lead

• US 20040153860A1
• Filed: 10/22/2003
• Published: 08/05/2004
• Est. Priority Date: 06/30/1989
• Status: Active Grant

• Current Assignee: Lee Doyle Whetsel
• Original Assignee: Lee Doyle Whetsel
• Inventors: Whetsel, Lee Doyle
• Granted Patent: US 7,058,871 B2
• Time in Patent Office: Days
• US Class Current: 714/43
• CPC Class Codes: G01R 31/31855 Interconnection testing, e.g. crosstalk, shortcircuits
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318569 Error indication, logging circuits
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults

Abstract

A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching condition the EOM (32) may perform a variety of tests on incoming data while the integrated circuits (10, 12) continue to operate at speed. A plurality of digital bus monitors (20, 22) may be cascaded for observation and test of variable width data buses and variable width signature analysis.

Claims

1. A digital bus monitor device for observing data on a bus connected to a plurality of devices comprising:

input circuitry for receiving data from the bus;

test circuitry connected to said input circuitry for storing data in response to a predetermined condition while the devices are in a functioning mode.

2. The digital bus monitor of claim 1 wherein said test circuitry comprises:

event qualification circuitry connected to said input circuitry to indicate when said predetermined condition has occurred.

3. The digital bus monitor of claim 2 wherein said test circuitry further comprises an expected data memory for storing a plurality of expected data words associated with said predetermined condition.

4. The digital bus monitor of claim 3 wherein said test circuitry is operable to compare said expected data word with data words received from said circuitry and is operable to indicate whether said received data matches said expected data word.

5. The digital bus monitor of claim 4 wherein said test circuitry further comprises a masking data memory for storing a masking data word associated with said expected data word, said masking data word identifying portions of said expected data word where matching is not required for a matching indication.

6. The digital bus monitor of claim 2 wherein said test circuitry is operable to perform signature analysis on said incoming data from the bus in response to said predetermined condition.

7. The digital bus monitor of claim 6 wherein said test circuitry is further operable to selectively mask portions of said incoming data from the bus to identify the source of an error after an incorrect signature has been detected.

8. The digital bus monitor of claim 5 wherein said expected data memory comprises a plurality of memory locations for storing respective expected data words.

9. The digital bus monitor of claim 1 and further comprising scan path circuitry for serially transferring data stored in the monitor to an external controller for inspection.

10. The digital bus monitor of claim 1 wherein said test circuitry further comprises a test memory buffer to store a plurality of data words from the bus responsive to said predetermined condition.

11. The digital bus monitor of claim 10 wherein said test memory buffer is operable to store a plurality of data words contemporaneously with signature analysis being performed on said plurality of data words by said test circuitry.

12. The digital bus monitor of claim 2 wherein said event qualification circuitry is operable to receive clock signals from one of a plurality of sources.

13. The digital bus monitor of claim 1 wherein said testing circuitry is operable to start storing data in response to a first predetermined condition and operable to stop storing data in response to a second predetermined condition.

14. The digital bus monitor of claim 13 wherein said testing circuitry is operable to resume storing data after a third predetermined condition and stop storing data after a fourth predetermined condition.

15. The digital bus monitor of claim 1 wherein said test circuitry comprises:

control circuitry to store data responsive to a selected protocol a predetermined number of times; and

counter circuitry to count the number of storage operations responsive to the protocol.

16. The digital bus monitor of claim 1 wherein said digital bus monitor further comprises cascade circuitry for cascading a plurality of digital bus monitoring devices.

17. A method of testing data transfers on a bus connected between a plurality of devices comprising the steps of:

receiving incoming data from the bus;

detecting the occurrence of a predetermined condition; and

processing input data in response to said predetermined condition while the integrated circuit is in the functioning mode.

18. The method of claim 17 wherein said step of detecting the predetermined condition comprises the step of comparing said incoming data with predetermined expected data.

19. The method of claim 17 wherein said processing step comprises the step of performing signature analysis on said incoming data.

20. The method of claim 19 and wherein said processing step further comprises the step of storing said incoming data in a memory buffer contemporaneously with said step of signature analysis.

21. The method of claim 19 and wherein said processing step further comprises the step of selectively masking one or more of the bits of said incoming data.

22. The method of claim 17 wherein said step of processing data comprises the step of storing data in sequential locations in a memory buffer.

23. The method of claim 22 and further comprising the step of ceasing to process said incoming data in response to a second predetermined condition.

24. The method of claim 23 and further comprising the step of resuming processing of incoming data in response to a third predetermined condition.