Delay management system

• US 20040153890A1
• Filed: 12/20/2002
• Published: 08/05/2004
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: Verigy Limited (Advantest Corporation)
• Original Assignee: Verigy Limited (Advantest Corporation)
• Inventors: Davis, Alan Howard, Freeseman, John
• Granted Patent: US 7,231,573 B2
• Time in Patent Office: Days
• US Class Current: 714/699
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

A delay management system in a computer system includes a delay manager and a first storage element that stores a delay time. The delay manager is configured to receive a series of delay values and respond to each delay value in the series of delay values by providing a corresponding delay time value. The delay time is updated to the corresponding delay time value if the corresponding delay time value is greater than the delay time.

Claims

1. A computer system, comprising:

a first storage element that stores a delay time; and

a delay manager configured to receive a series of delay values, respond to each delay value in the series of delay values by providing a corresponding delay time value, and update the delay time to the corresponding delay time value if the corresponding delay time value is greater than the delay time.

2. The computer system of claim 1, where the delay manager is configured to decrement the delay time and the corresponding delay time value is each delay value in the series of delay values.

3. The computer system of claim 2, where the delay manager is configured to provide a remaining time ready signal that indicates the delay time has reached zero.

4. The computer system of claim 2, where the delay manager is configured to provide the delay time in response to an instruction to provide the remaining time.

5. The computer system of claim 1, where the delay manager is configured to accept a user supplied delay value.

6. The computer system of claim 1, further comprising a timer that provides a current time, where the delay manager is configured to respond to each delay value in the series of delay values by retrieving a corresponding current time value, and provide a combination of each delay value in the series of delay values and the retrieved corresponding current time value as the corresponding delay time value.

7. The computer system of claim 6, where the delay manager is configured to provide a settling time ready signal that indicates the current time has reached the delay time.

8. The computer system of claim 6, further comprising a second storage element that stores a current start time, where the delay manager is configured to update the current start time to the retrieved corresponding current time value used to update the delay time, retrieve current time values and compare the retrieved current time values to the current start time and the delay time to detect timer wrap around.

9. The computer system of claim 6, further comprising a second storage element that stores a current start time, where the delay manager is configured to update the current start time to the retrieved corresponding current time value used to update the delay time and provide a wait signal that indicates the current time is between the current start time and the delay time.

10. The computer system of claim 6, further comprising a third storage element that stores a remaining time, where the delay manager is configured to update the remaining time to each delay value in the series of delay values used to update the delay time, and decrement the remaining time to provide a remaining time ready signal that indicates the remaining time has reached zero.

11. The computer system of claim 10, where the delay manager is configured to provide the remaining time in response to an instruction to provide the remaining time.

12. The computer system of claim 10, where the delay manager is configured to set the remaining time to zero in response to an instruction to set the remaining time to zero.

13. The computer system of claim 10, where the delay manager is configured to wait until the remaining time has reached zero to continue processing in response to a wait instruction.

14. The computer system of claim 10, further comprising a fourth storage element that stores a cumulative wait total, where the delay manager is configured to update the cumulative wait total to the sum of the remaining time and the cumulative wait total each time the computer system must wait to execute a test.

15. The computer system of claim 14, where the delay manager is adapted to provide the cumulative wait total in response to an instruction to provide the cumulative wait total.

16. The computer system of claim 14, where the delay manager is adapted to set the cumulative wait total to zero in response to an instruction to set the cumulative wait total to zero.

17. A computer system, comprising:

a timer that provides a current time;

memory storing a delay time and a delay manager program that has retrieving instructions, providing instructions and updating instructions; and

a processor that executes the delay manager program, wherein the processor executes the retrieving instructions to receive a series of delay values and respond to each delay value in the series of delay values by retrieving a corresponding current time value, where the processor executes the providing instructions to provide a corresponding delay time value that is a combination of each delay value in the series of delay values and the retrieved corresponding current time value, where the processor executes the updating instructions to update the delay time to the corresponding delay time value if the corresponding delay time value is greater than the delay time.

18. A method for managing delays in a computer system, comprising:

receiving a series of delay values;

providing a corresponding delay time value in response to each delay value in the series of delay values; and

updating a delay time stored in a storage device to the corresponding delay time value if the corresponding delay time value is greater than the delay time.

19. The method of claim 18, further comprising;

retrieving a corresponding current time value from a timer in response to each delay value in the series of delay values;

providing a combination of each delay value in the series of delay values and the retrieved corresponding current time value as the corresponding delay time value; and

providing a settling time ready signal that indicates the current time has reached the delay time.

20. The method of claim 18, further comprising;

decrementing the delay time;

providing each delay value in the series of delay values as the corresponding delay time value; and

providing a remaining time ready signal that indicates the delay time has reached zero.