Serial flash integrated circuit having error detection and correction

• US 20040153902A1
• Filed: 01/21/2003
• Published: 08/05/2004
• Est. Priority Date: 01/21/2003
• Status: Abandoned Application

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: NexFlash Technologies, Inc. (Winbond Electronics Corporation)
• Inventors: Machado, Michael G., Van Genderen, Chris, Park, Joo Weon, Lee, Poongyeub
• Application Number:
  US10/349,748
• Publication Number:
  US 20040153902A1
• Time in Patent Office: Days
• US Class Current: 714/710
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory

Abstract

A serial flash integrated circuit is provided with an integrated error correction coding (“ECC”) system that is used with an integrated volatile page memory for fast automatic data correction. The ECC code has the capability of correcting any one or two bit errors that might occur on a page of the flash memory array. One bit corrections are done automatically in hardware during reads or transfer to the page memory, while two-bit corrections are handled in external software, firmware or hardware. The ECC system uses a syndrome generator for generating both write and read syndromes, and an error trapper to identify the location of single bit errors using very little additional chip space. The flash memory array may be refreshed from the page memory to correct any detected errors. Data status is made available to the application prior to the data. The use of the ECC is optional.

Claims

1. An integrated circuit operable in an ECC memory write mode and an ECC memory read mode, comprising:

a data path disposed in the integrated circuit;

a flash memory array disposed in the integrated circuit and coupled to the data path;

an ECC circuit disposed in the integrated circuit and coupled to the data path for;

creating from first data a single large write codeword using a bit-correcting ECC code during the ECC write mode; and

generating a read syndrome from a read codeword using the bit-correcting ECC code during the FCC read mode; and

a data interface coupled to the data path for furnishing the first data thereto during the ECC write mode.

2. The integrated circuit of claim 1 wherein the ECC circuit comprises a sequential FCC detection engine having a bit-serial coupling to the data path.

3. The integrated circuit of claim 2 wherein the ECC detection engine comprises:

a single syndrome generator coupled to the data path and configurable during the write mode for creating the write codeword from the first data, and configurable during the read mode for generating the read syndrome from the read codeword; and

an error trapper coupled to the syndrome generator.

4. The integrated circuit of claim 3 wherein the syndrome generator uses a BCH ECC code.

5. The integrated circuit of claim 2 wherein the ECC detection engine comprises:

a write syndrome generator coupled to the data path for creating the write codeword from the first data during the write mode;

a read syndrome generator coupled to the data path for generating the read syndrome from the read codeword during the read mode; and

an error trapper coupled to the read syndrome generator.

6. The integrated circuit of claim 1 wherein the ECC circuit comprises a sequential ECC detection and correction engine having a bit-serial coupling to the data path.

7. The integrated circuit of claim 6 wherein the ECC correction engine comprises:

a single syndrome generator coupled to the data path and configurable during the write mode for creating the write codeword from the first data, and configurable during the read mode for generating the read syndrome from the read codeword;

an error trapper coupled to the syndrome generator;

a counter;

a sequencer coupled to the error trapper and the counter, and further coupled to the data path for furnishing an error status indicator;

address logic coupled to the counter; and

a bit inverter coupled to the address logic and to the data path.

8. The integrated circuit of claim 7 wherein the syndrome generator uses a BCH ECC code.

9. The integrated circuit of claim 1 wherein the flash memory comprises a plurality of memory pages of a predetermined page size, the write and read codewords being of a size equal or substantially equal to the page size, and the first data being of a size less than the page size.

10. The integrated circuit of claim 1 wherein the data path is further configurable in an non-ECC write mode and a non-ECC read mode.

11. The integrated circuit of claim 10 wherein:

the flash memory comprises a plurality of memory pages of a predetermined page size, the write and read codewords being of a size equal or substantially equal to the page size and the first data being of a size less than the page size; and

the data interface circuit further is coupled to the data path for furnishing thereto second data of a size equal or substantially equal to the page size during the non-ECC write mode.

12. The integrated circuit of claim 10 wherein:

the flash memory comprises a plurality of memory pages of a predetermined page size, the write and read codeword being of a size equal or substantially equal to the page size and the first data being of a size less than the page size; and

the data interface circuit further is coupled to the data path for furnishing thereto second data of a size equal to the size of the first data during the non-ECC write mode.

13. The integrated circuit of claim 1 wherein the data interface comprises a bit-serial input/output circuit.

14. The integrated circuit of claim 1 wherein the data interface comprises a parallel-to-serial input circuit and a serial-to-parallel output circuit.

15. The integrated circuit of claim 1 further comprising a page memory disposed in the integrated circuit and coupled to the data path.

16. An integrated circuit operable in an ECC memory write mode and an ECC memory read mode, comprising:

a data path disposed in the integrated circuit;

a flash memory array disposed in the integrated circuit and coupled to the data path;

an ECC circuit disposed in the integrated circuit and coupled to the data path for;

creating from first data a single large write codeword during the ECC write mode; and

generating a read syndrome from a read codeword during the ECC read mode; and

a bit-serial data interface coupled to the data path for furnishing the first data thereto during the ECC write mode.

17. The integrated circuit of claim 16 wherein the ECC circuit comprises a sequential ECC detection engine using a bit-correcting ECC code and having a bit-serial coupling to the data path.

18. The integrated circuit of claim 16 wherein the ECC circuit comprises a sequential ECC detection and correction engine using a bit-correcting ECC code and having a bit-serial coupling to the data path.

19. The integrated circuit of claim 18 wherein the bit-correcting ECC code is a BCH ECC code.

20. A method of correcting erroneous data in an integrated circuit having a flash memory array, comprising:

receiving binary data;

creating a single large codeword from the data with a bit-correcting ECC code;

programming the codeword into the flash memory array;

reading the codeword from the flash memory array;

generating a read syndrome from the codeword read in the reading step;

evaluating the read syndrome to determine a condition of the codeword read in the reading step; and

when the codeword condition is an error condition, attempting to correct the error condition internally in the integrated circuit as determined by the read syndrome.

21. The method of claim 20 wherein the attempting step is at least in part performed in a hardware error trapper disposed in the integrated circuit.

22. The method of claim 20 wherein the error condition is a small error condition, further comprising:

successfully completing the attempting step to obtain a corrected codeword internally in the integrated circuit; and

furnishing a recovered form of the data from the corrected codeword as an output of the integrated circuit.

23. The method of claim 20 wherein the error condition is a large error condition, further comprising:

unsuccessfully completing the attempting step; and

furnishing information suitable for enabling off-chip recovery of the data from the codeword read in the reading step, as an output of the integrated circuit.

24. The method of claim 23 wherein the information furnished as the output of the integrated circuit comprises the codeword read in the reading step.

25. The method of claim 23 wherein the information furnished as the output of the integrated circuit comprises the codeword read in the reading step and the read syndrome.

26. The method of claim 23 wherein the information furnished as the output of the integrated circuit comprises a data section of the codeword read in the reading step and the read syndrome.

27. The method of claim 20 wherein:

the flash memory array comprises a plurality of memory pages of a predetermined page size, the codewords programmed in the programming step and read in the reading step being of a size equal or substantially equal to the page size and the data being of a size less than the page size; and

the error condition is internally correctable in the integrated circuit for a one bit error, and is externally correctable for at least a two bit error.

28. The method of claim 20 wherein the data receiving step comprises receiving the data in a bit-serial manner.

29. A method of storing user data in and retrieving user data from a nonvolatile page-mode memory array disposed in an integrated circuit and having a plurality of pages of a common size, comprising:

determining within the integrated circuit a single ECC codeword from successive bits of data using a bit-correcting ECC code, the ECC codeword being of a size equal or substantially equal to the page size and comprising the data and a write syndrome;

storing the ECC codeword in a page of the nonvolatile memory array by page mode programming;

reading the ECC codeword from the page of the flash memory array;

calculating within the integrated circuit a read syndrome from the ECC codeword read in the reading step; and

performing within the integrated circuit an error trapping operation using the read syndrome.

30. The method of claim 29:

wherein the error trapping operation performing step comprises generating within the integrated circuit an error location;

further comprising correcting within the integrated circuit an error at the error location in the ECC codeword read in the reading step.

31. The method of claim 29 wherein:

the reading step comprises reading the ECC codeword from the page of the flash memory array to a volatile memory in the integrated circuit having substantially a page of storage capacity; and

the calculating step comprises calculating the read syndrome from the ECC codeword in the volatile memory.

32. The method of claim 29 further comprising acquiring the data through a bit-serial interface.

33. A method of storing user data in and retrieving user data from a flash memory array that is part of a serial flash integrated circuit, comprising:

calculating a write syndrome in the serial flash integrated circuit from successive bits of the user data with a bit-correcting ECC code;

storing the user data and the ECC write syndrome in a page of the flash memory array as an ECC codeword;

reading the ECC codeword from the page of the flash memory array to a volatile memory having essentially a page of storage capacity, the volatile memory being part of the serial flash integrated circuit;

calculating a read syndrome from the ECC codeword read in the reading step;

detecting a one bit error and location information therefor from the read syndrome; and

correcting the one bit error in the volatile memory by use of the location information.

34. The method of claim 33 wherein:

the serial flash integrated circuit comprises a syndrome generator; and

the ECC syndrome calculating step and the read syndrome calculating step are performed in the syndrome generator.

35. A method of correcting erroneous data in an integrated circuit having a flash memory array, comprising:

receiving binary data in bit-serial form;

creating a single large codeword from the data;

programming the codeword into the flash memory array;

reading the codeword from the flash memory array;

generating a read syndrome from the codeword read in the reading step;

evaluating the read syndrome to determine a condition of the codeword; and

when the codeword condition is an error condition, attempting to correct the error condition internally in the integrated circuit as determined by the read syndrome.

36. The method of claim 35 wherein the attempting step is at least in part performed in a hardware error trapper disposed in the integrated circuit.

37. The method of claim 35 wherein the error condition is a small error condition, further comprising:

successfully completing the attempting step to obtain a corrected codeword internally in the integrated circuit; and

furnishing a recovered form of the data from the corrected codeword as an output of the integrated circuit.

38. The method of claim 35 wherein the error condition is a large error condition, further comprising:

unsuccessfully completing the attempting step; and

furnishing information suitable for enabling off-chip recovery of the data from the codeword read in the reading step, as an output of the integrated circuit.

39. The method of claim 38 wherein the information furnished as the output of the integrated circuit comprises the codeword read in the reading step.

40. The method of claim 38 wherein the information furnished as the output of the integrated circuit comprises the codeword read in the reading step and the read syndrome.

41. The method of claim 38 wherein the information furnished as the output of the integrated circuit comprises a data section of the codeword read in the reading step and the read syndrome.

42. The method of claim 35 wherein:

the flash memory array comprises a plurality of memory pages of a predetermined page size, the codewords programmed in the programming step and read in the reading step being of a size equal or substantially equal to the page size and the data being of a size less than the page size; and

the error condition is internally correctable in the integrated circuit for a one bit error, and is externally correctable for at least a two bit error.

43. The method of claim 35 wherein the large codeword creating step comprises creating the single large codeword from sequential bits of the data with a bit-correcting ECC code.

44. An integrated circuit operable in an ECC memory write mode and an ECC memory read mode, comprising:

a data path disposed in the integrated circuit;

a data interface coupled to the data path for furnishing data thereto during the ECC write mode;

a flash memory array disposed in the integrated circuit and coupled to the data path; and

a bit-correcting sequential ECC correction engine disposed in the integrated circuit and coupled to the data path for;

sequentially receiving the data in bit-serial fashion and furnishing a write codeword derived from the data during the ECC write mode; and

sequentially receiving a read codeword, furnishing an error status indication based at least in part on an evaluation of a read syndrome derived from the read codeword during the ECC read mode, and correcting an error condition in the read codeword.

45. The integrated circuit of claim 44 wherein the ECC correction engine comprises:

a single syndrome generator coupled to the data path and configurable during the write mode for creating the write codeword from the first data, the write codeword being a single large codeword, and configurable during the read mode for generating the read syndrome from the read codeword; and

an error trapper coupled to the syndrome generator.

46. The integrated circuit of claim 45 wherein the single syndrome generator has a bit-serial coupling to the data path.

47. The integrated circuit of claim 45 wherein the syndrome generator uses a BCH ECC code.

48. The integrated circuit of claim 44 wherein the ECC correction engine comprises:

a single syndrome generator having a bit-serial coupling to the data path and configurable during the write mode for creating the write codeword from the first data, the write codeword being a single large codeword, and configurable during the read mode for generating the read syndrome from the read codeword;

an error trapper coupled to the syndrome generator;

a counter;

a sequencer coupled to the error trapper and the counter, and further coupled to the data path for furnishing an error status indicator;

address logic coupled to the counter; and

a bit inverter coupled to the address logic and to the data path.

49. The integrated circuit of claim 44 wherein the data interface comprises a bit-serial input/output circuit.

50. The integrated circuit of claim 44 further comprising a page memory disposed in the integrated circuit and coupled to the data path.

51. An integrated circuit comprising:

a data path disposed in the integrated circuit;

a bit-serial interface disposed in the integrated circuit and coupled to the data path;

a flash memory array disposed in the integrated circuit and coupled to the data path; and

a sequential correction engine having a bit-serial coupling to the data path, the correction engine using a bit-correcting ECC code to create a codeword and to generate a read syndrome from a codeword.

52. The integrated circuit of claim 51 wherein the correction engine uses a bit-correcting ECC code to create a single large write codeword and to generate a read syndrome from a single large read codeword.

53. The integrated circuit of claim 52 wherein:

the flash memory array is a page mode memory having a plurality of pages of a common page size; and

the write and read codewords are of a size equal or substantially equal to the page size.

54. A method of correcting erroneous data in an integrated circuit having a flash memory array, comprising:

receiving binary data in the integrated circuit;

sequentially processing bits of the data with a bit-correcting ECC code in the integrated circuit to create a codeword;

programming the codeword into the flash memory array;

reading the codeword from the flash memory array;

sequentially processing the codeword read in the reading step with the bit-correcting ECC code in the integrated circuit to generate a read syndrome;

evaluating the read syndrome to determine a condition of the codeword; and

when the codeword condition is an error condition, sequentially processing the codeword read in the reading step as determined by the read syndrome in an attempt to correct the error condition internally in the integrated circuit.

55. The method of claim 54 wherein the receiving step comprises receiving the binary data in the integrated circuit in a bit-serial manner.

56. The method of claim 54 further comprising successfully completing the step of sequentially processing the codeword read in the reading step as determined by the read syndrome when the error condition is a small error condition, whereby the error condition is corrected internally in the integrated circuit.

57. The method of claim 54 further comprising unsuccessfully completing the step of sequentially processing the codeword read in the reading step as determined by the read syndrome when the error condition is a large error condition.

58. A method of refreshing a flash memory array that is part of an integrated circuit, comprising:

reading an ECC codeword from a page of the flash memory array to a volatile memory having essentially a page of storage capacity, the volatile memory being part of the integrated circuit;

calculating a read syndrome from the ECC codeword, in the integrated circuit;

detecting an error condition in the ECC codeword and location information therefor from, at least in part, the read syndrome, in the integrated circuit;

correcting the error condition in the ECC codeword residing in the volatile memory by use of the location information, in the integrated circuit, to obtain a corrected ECC codeword having one or more corrected bit or bits; and

writing at least the corrected bit or bits of the corrected ECC codeword from the volatile memory to a page of the flash memory array.

59. The method of claim 58 further comprising:

obtaining data from the corrected ECC codeword residing in the volatile memory; and

furnishing the data to an application.

60. The method of claim 58 wherein the reading, calculating, detecting, correcting, and writing steps are performed as an internal background task.

61. The method of claim 58 wherein the reading, calculating, detecting, correcting, and writing steps are performed in response to a command from an application.

62. The method of claim 59 wherein the writing step is performed automatically after the correcting step.

63. The method of claim 59 further comprising:

reporting the error condition to the application; and

receiving a command from the application to refresh the flash memory array;

wherein the writing step is performed in response to the command in the receiving step.

64. The method of claim 58 wherein the writing step comprises writing the entire corrected ECC codeword.

65. A method of refreshing a flash memory array that is part of an integrated circuit, comprising:

reading an ECC codeword from a page of the flash memory array;

calculating a read syndrome from the ECC codeword, in the integrated circuit;

detecting an error condition in the ECC codeword and location information therefor from, at least in part, the read syndrome, in the integrated circuit;

correcting the error condition in the ECC codeword, in the integrated circuit, to obtain an ECC codeword having one or more corrected bit or bits; and

writing at least the corrected bit or bits of the ECC codeword to a page of the flash memory array.

66. The method of claim 65 wherein the reading, calculating, detecting, correcting, and writing steps are performed as an internal background task.

67. The method of claim 65 wherein the reading, calculating, detecting, correcting, and writing steps are performed in response to a command from an application.

68. The method of claim 65 wherein the writing step is performed automatically during memory read mode, after the correcting step.

69. The method of claim 65 further comprising:

reporting the error condition to the application; and

receiving a command from the application to refresh the flash memory array;

wherein the writing step is performed in response to the command in the receiving step.

70. A method of obtaining data from the flash memory array of an integrated circuit, comprising:

reading a plurality of ECC codewords from respective pages of the flash memory array in the integrated circuit, each of the ECC codewords comprising a data section and an ECC write syndrome section;

generating, in the integrated circuit, respective read syndromes from the ECC codewords, wherein some of the read syndromes indicate no erroneous data and others of the read syndromes indicate erroneous data;

attempting correction of the ECC codewords having respective read syndromes indicating erroneous data, in the integrated circuit;

for the ECC codewords successfully corrected in the correction attempting step, furnishing the data sections thereof as outputs from the integrated circuit;

for the ECC codewords unsuccessfully corrected in the correction attempting step, furnishing information suitable for off-chip recovery of data therefrom as outputs from the integrated circuit; and

for the ECC codewords having respective read syndromes indicating no erroneous data, furnishing the data sections thereof as outputs from the integrated circuit.

71. The method of claim 70 further comprising:

for the ECC codewords successfully corrected in the correction attempting step, reporting corrected error status prior to the step of furnishing the data sections thereof;

for the ECC codewords unsuccessfully corrected in the correction attempting step, reporting uncorrected error status prior to the step of furnishing the data sections thereof and the respective read syndromes; and

for the ECC codewords having respective read syndromes indicating no erroneous data, reporting no-error status prior to the step of furnishing the data sections thereof.

72. The method of claim 70 further comprising, for the ECC codewords successfully corrected in the correction attempting step, programming the corrected ECC codewords into respective pages of the flash memory array.

73. The method of claim 70 wherein the information furnished as the output of the integrated circuit for the ECC codewords unsuccessfully corrected in the correction attempting step comprises the ECC codewords unsuccessfully corrected in the correction attempting step.

74. The method of claim 70 wherein the information furnished as the output of the integrated circuit for the ECC codewords unsuccessfully corrected in the correction attempting step comprises the ECC codewords unsuccessfully corrected in the correction attempting step and the read syndromes generated therefrom.

75. The method of claim 70 wherein the information furnished as the output of the integrated circuit for the ECC codewords unsuccessfully corrected in the correction attempting step comprises data sections of the ECC codewords unsuccessfully corrected in the correction attempting step and the read syndromes generated therefrom.

76. A method of writing to the flash memory array of an integrated circuit, comprising:

serially receiving first data and a first command to write the first data without error correction;

programming a page of the flash memory array with the first data;

serially receiving second data and a second command to write the second data with error correction;

generating an ECC codeword from the second data; and

programming a page of the flash memory array with the ECC codeword.

77. The method of claim 76 wherein the generating step comprises:

generating an ECC write syndrome from the second data; and

combining the ECC write syndrome with the second data to form the ECC codeword.

78. A method of reading the flash memory array of an integrated circuit, comprising:

serially receiving a first command to read a first page of the flash memory array without error correction;

furnishing the first page of the flash memory array as serial output from the integrated circuit;

serially receiving a second command to read a second page of the flash memory array with error correction;

generating in the integrated circuit a read syndrome from an ECC codeword stored in the second page of the flash memory, the ECC codeword having a data section and a write syndrome section;

evaluating the read syndrome in the integrated circuit to detect an error condition in the ECC codeword;

correcting the error condition in the ECC codeword as determined by the read syndrome in the integrated circuit to obtain a corrected ECC codeword; and

furnishing the data section of the corrected first ECC codeword as output from the integrated circuit.

79. A method of correcting erroneous data in an integrated circuit having a flash memory array, comprising:

reading a codeword from the flash memory array, the codeword comprising data and a write syndrome;

generating a read syndrome in the integrated circuit from the codeword read in the reading step;

evaluating the read syndrome to determine whether an error condition exists in the codeword;

furnishing the data from the codeword as output from the integrated circuit based on the evaluating step, the data being uncorrected when the evaluating step indicates no error condition, the data being corrected based on the read syndrome when the evaluating step indicates an error condition and the error condition is correctable, and the data being uncorrected when the evaluating step indicates an error condition and the error condition is uncorrectable; and

prior to the data furnishing step, furnishing a data status as output from the integrated circuit, the data status being “

error free”

when the evaluating step indicates no error condition, the data status being “

corrected error”

when the evaluating step indicates an error condition and the error condition is correctable, and the data status being “

uncorrectable error”

when the evaluating step indicates an error condition and the error condition is uncorrectable.

80. A serial flash memory integrated circuit comprising:

a data path;

a flash memory array coupled to the data path;

a page memory coupled to the data path;

a bit-serial input/output interface coupled to the data path;

a sequential syndrome generator based on a bit-correcting ECC code having a bit-serial coupling to the data path and an output; and

an error trapper having an input coupled to the output of the syndrome generator.

81. A serial flash memory integrated circuit comprising:

a flash memory array;

a page memory coupled to the flash memory array;

a shift register coupled to the flash memory array and to the page memory;

a bit inverter coupled to the shift register;

a bit-serial input/output interface coupled to the shift register;

a sequential syndrome generator based on a bit-correcting ECC code and having a bit-serial coupling to the shift register and an output;

an error trapper having an input coupled to the output of the syndrome generator;

a zero detector coupled to the output of the syndrome generator;

a counter;

a sequencer coupled to the error trapper, the zero detector, and the counter, and having an error status output coupled to the input/output interface; and

address logic having an input coupled to the counter and an output coupled to the bit inverter.