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Three-dimensional-memory-based self-test integrated circuits and methods

  • US 20040155301A1
  • Filed: 02/03/2004
  • Published: 08/12/2004
  • Est. Priority Date: 10/07/2001
  • Status: Active Grant
First Claim
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1. An integrated circuit (IC) supporting non-electrically-programmable three-dimensional memory (NEP-3DM)-based self-test (NEP-3DMST), comprising a substrate circuit, said substrate circuit further comprising a circuit-under-test (CUT) and a peripheral circuit;

  • and, at least an NEP-3DM level stacked on said substrate circuit, at least a portion of said NEP-3DM level storing at least a portion of test data and/or test-data seeds for said CUT and being connected with said peripheral circuit through a plurality of inter-level connecting vias.

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