Circuits and methods to protect a gate dielectric antifuse
First Claim
Patent Images
1. An integrated circuit, comprising:
- an antifuse including a first terminal, a second terminal and a gate dielectric between the first terminal and the second terminal, the first terminal being connected to a line;
a program driver circuit coupled to the second terminal of the antifuse; and
a bypass circuit coupled to the line and the program driver circuit, the bypass circuit being adapted to shunt current around the antifuse during a programming mode.
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Abstract
According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse, controlling current in the antifuse with a program driver circuit coupled to a second terminal of the antifuse, and shunting current around the antifuse with a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to protect the antifuse. The antifuse includes a layer of gate dielectric between the first terminal and the second terminal. The embodiments of the present invention protect a gate dielectric antifuse.
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Citations
32 Claims
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1. An integrated circuit, comprising:
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an antifuse including a first terminal, a second terminal and a gate dielectric between the first terminal and the second terminal, the first terminal being connected to a line;
a program driver circuit coupled to the second terminal of the antifuse; and
a bypass circuit coupled to the line and the program driver circuit, the bypass circuit being adapted to shunt current around the antifuse during a programming mode. - View Dependent Claims (2, 3, 4, 5)
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6. An integrated circuit, comprising:
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a line to provide a programming voltage during a programming mode and to provide a common voltage during a non-programming mode;
an antifuse including a first terminal connected to the line, a second terminal and a gate dielectric between the first terminal and the second terminal;
a program driver circuit coupled to the second terminal of the antifuse; and
a bypass circuit coupled to the line and the program driver circuit in parallel with the antifuse, the bypass circuit being adapted to shunt current around the antifuse during the programming mode with the antifuse not being selected to be blown. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. An integrated circuit, comprising:
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an antifuse including a first terminal, a second terminal and a gate dielectric between the first terminal and the second terminal and including a silicide, the first terminal being connected to a line;
a program driver circuit coupled to the second terminal of the antifuse; and
a bypass circuit coupled to the line and the program driver circuit, the bypass circuit being adapted to shunt current around the antifuse during a programming mode. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. An integrated circuit, comprising:
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an antifuse including a first terminal, a second terminal and a gate dielectric between the first terminal and the second terminal, the first terminal being connected to a line;
a program driver circuit coupled to the second terminal of the antifuse;
a gate bias circuit connected to the program driver circuit; and
a bypass circuit coupled to the line and the program driver circuit, the bypass circuit being adapted to shunt current around the antifuse during a programming mode. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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28. An integrated circuit, comprising:
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an antifuse including a first terminal, a second terminal and a gate dielectric between the first terminal and the second terminal, the first terminal being connected to a line;
a program driver circuit coupled to the second terminal of the antifuse;
a bypass circuit coupled to the line and the program driver circuit, the bypass circuit being adapted to shunt current around the antifuse during a programming mode; and
wherein the program driver circuit includes a first transistor, second transistor and third transistor connected in series. - View Dependent Claims (29, 30, 31, 32)
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Specification