TFT-based random access memory cells comprising thyristors

• US 20040156233A1
• Filed: 02/10/2003
• Published: 08/12/2004
• Est. Priority Date: 02/10/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup
• Granted Patent: US 6,812,504 B2
• Time in Patent Office: Days
• US Class Current: 365/176
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

The invention includes SOI constructions containing one or more memory cells which include a transistor and a thyristor. In one aspect, a scalable GLTRAM cell provides DRAM-like density and SRAM-like performance. The memory cell includes an access transistor and a gated-lateral thyristor integrally formed above the access transistor. The cathode region (n+) of the stacked lateral thyristor device (p+/n/p/n+) is physically and electrically connected to one of the source/drain regions of the FET to act as the storage node for the memory cell. The FET transistor can include an active region which extends into a Si/Ge material. The material comprising Si/Ge can have a relaxed crystalline lattice, and a layer having a strained crystalline lattice can be between the material having the relaxed crystalline lattice and the transistor gate. The device construction can be formed over a versatile substrate base.

Claims

1. A memory cell construction, comprising:

an electrically insulative material;

a crystalline layer comprising silicon and germanium over the electrically insulative material;

an access transistor device having an active region extending into the crystalline layer;

the entirety of the active region within the crystalline layer being within only a single crystal of the crystalline layer;

the transistor device including a gate and a source region; and

a thyristor electrically connected with the source region.

2. The construction of claim 1 wherein the transistor gate is over the crystalline layer and wherein the source region is entirely beneath the transistor gate.

3. The construction of claim 1 wherein the source region comprises a raised source portion;

and wherein the thyristor is a lateral thyristor above the transistor device and has a first end in physical contact with the raised source portion.

4. The construction of claim 1 wherein the crystalline layer comprises from about 10 to about 60 atomic percent germanium.

5. The construction of claim 1 wherein the crystalline layer is polycrystalline.

6. The construction of claim 1 wherein the crystalline layer is monocrystalline.

7. The construction of claim 1 wherein the crystalline layer has a relaxed crystalline lattice, and further comprising a strained crystalline lattice layer between the crystalline layer and the transistor device gate.

8. The construction of claim 7 herein the strained crystalline lattice includes silicon.

9. The construction of claim 7 wherein the strained crystalline lattice includes silicon and germanium.

10. The construction of claim 1 wherein the transistor device is an NFET device.

11. The construction of claim 1 wherein the transistor device is a PFET device.

12. The construction of claim 1 wherein the electrically insulative material is supported by a substrate;

and wherein the crystalline layer and electrically insulative material are together comprised by an SOI construction.

13. The construction of claim 12 wherein the substrate comprises a semiconductive material.

14. The construction of claim 12 wherein the substrate comprises glass.

15. The construction of claim 12 wherein the substrate comprises aluminum oxide.

16. The construction of claim 12 wherein the substrate comprises silicon dioxide.

17. The construction of claim 12 wherein the substrate comprises a metal.

18. The construction of claim 12 wherein the substrate comprises a plastic.

19. A semiconductor-on-insulator construction, comprising:

a substrate;

an insulator layer over the substrate;

a crystalline layer comprising silicon and germanium over the insulator layer;

a transistor device supported by the crystalline layer, the transistor device comprising a gate and an active region proximate the gate;

the active region including a channel region;

at least a portion of the active region being within the crystalline layer;

an entirety of the active region within the crystalline layer being within a single crystal of the crystalline layer;

the transistor device comprising a pair of source/drain regions; and

a thyristor electrically connected within one of the source/drain regions of the transistor device.

20. The construction of claim 19 wherein:

the transistor device is an NFET device and said one of the source/drain regions is an n+ source region;

the thyristor is a p+/n/p/n+ thyristor; and

a cathode of the thyristor physically contacts the n+ source region.

21. The construction of claim 20 wherein the n+ source region extends vertically over the crystalline layer;

and wherein the thyristor extends horizontally.

22. The construction of claim 19 wherein the crystalline layer has a relaxed crystalline lattice, and further comprising a strained crystalline lattice layer between the crystalline layer and the transistor device gate.

23. The construction of claim 22 wherein the strained crystalline lattice layer includes silicon.

24. The construction of claim 22 wherein the strained crystalline lattice layer includes silicon and germanium.

25. The construction of claim 19 wherein the insulator layer consists of silicon dioxide.

26. The construction of claim 19 wherein the entirety of the crystalline layer is a single crystal.

27. The construction of claim 19 wherein the crystalline layer is polycrystalline.

28. The construction of claim 19 wherein the crystalline layer is in physical contact with the insulator layer.

29. The construction of claim 19 wherein the crystalline layer consists of silicon and germanium.

30. The construction of claim 29 wherein the crystalline layer comprises from about 10 to about 60 atomic percent germanium.

31. The construction of claim 19 wherein the substrate comprises a semiconductive material.

32. The construction of claim 19 wherein the substrate comprises glass.

33. The construction of claim 19 wherein the substrate comprises aluminum oxide.

34. The construction of claim 19 wherein the substrate comprises silicon dioxide.

35. The construction of claim 19 wherein the substrate comprises a metal.

36. The construction of claim 19 wherein the substrate comprises a plastic.

37. A memory device comprising:

a transistor having a gate supported by a crystalline layer and having a pair of source/drain regions proximate the gate;

the crystalline layer being less than or equal to about 2000 Å

thick;

the crystalline layer comprising a material which includes silicon and germanium;

the transistor having an active region;

at least a portion of the active region being within the material;

the active region within the material being contained within a single crystal of the material; and

a thyristor electrically connected with one of the source/drain regions.

38. The construction of claim 37 wherein:

the transistor device is an NFET device and said one of the source/drain regions is an n+ source region;

the thyristor is a p+/n/p/n+ thyristor; and

a cathode of the thyristor physically contacts the n+ source region.

39. The construction of claim 38 wherein the n+ source region extends vertically over the crystalline layer;

and wherein the thyristor extends horizontally.

40. The memory device of claim 37 wherein the crystalline layer is polycrystalline.

41. The memory device of claim 37 wherein the crystalline layer is monocrystalline.

42. The memory device of claim 37 wherein the crystalline layer has a relaxed crystalline lattice, and further comprising a strained crystalline lattice layer between the crystalline layer and the transistor gate.

43. The memory device of claim 42 wherein the strained crystalline lattice includes silicon.

44. The memory device of claim 42 wherein the strained crystalline lattice includes silicon and germanium.

45. An electronic system, the electronic system comprising a memory device, the memory device including:

an array of memory cells, at least some of the memory cells including transistors and thyristors;

the transistors having gates supported by a crystalline layer;

the crystalline layer being less than or equal to about 2000 Å

thick;

the crystalline layer comprising a material which includes silicon and germanium;

the at least some of the transistors having active regions within the crystalline layer;

each active region within the crystalline layer including only one crystal of said material;

addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and

a read circuit coupled to the memory cell array for reading data from memory cells in the array of memory cells.

46. The electronic system of claim 45 wherein:

the transistor devices are NFET devices comprising n+ source regions;

the thyristors are p+/n/p/n+ thyristors; and

cathodes of the thyristors physically contact the n+ source regions.

47. The electronic system of claim 46 wherein the n+ source regions extend vertically over the crystalline layer;

and wherein the thyristors extend horizontally.

48. The electronic system of claim 45 wherein the crystalline layer is polycrystalline.

49. The electronic system of claim 45 wherein the crystalline layer is monocrystalline.

50. The electronic system of claim 45 wherein the crystalline layer has a relaxed crystalline lattice, and further comprising a strained crystalline lattice layer between the crystalline layer and the transistor gates.

51. The electronic system of claim 50 wherein the strained crystalline lattice includes silicon.

52. The electronic system of claim 50 wherein the strained crystalline lattice includes silicon and germanium.