Data transmission update technique in low power modes

• US 20040156396A1
• Filed: 02/07/2003
• Published: 08/12/2004
• Est. Priority Date: 02/07/2003
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Amick, Brian W., Gauthier, Claude R., Roy, Aninda
• Granted Patent: US 7,043,683 B2
• Time in Patent Office: Days
• US Class Current: 370/503
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: H04J 3/06 Synchronising arrangements for television systems H04N5/04; bit-synchronisation H04L7/00
• CPC Class Codes: H04L 7/0037 Delay of clock signal

Abstract

A data transmission update technique for use in a low power mode and/or a low activity mode of a computer system or a portion thereof is provided. When in the low power mode and/or the low activity mode, the technique initiates a testing of data transmissions, the results of which are used to adjust the timing of data receipt such that accurate and timely date communications are facilitated.

Claims

1. A computer system having at least a portion capable of operating in a normal mode and a low power mode, comprising:

a transmission link arranged to propagate a data signal and a clock signal; and

calibration circuitry, operatively connected to the clock signal and dependent on a power mode control signal, capable of updating a receipt time of the data signal,

wherein the power mode control signal is indicative of whether the at least a portion is in the low power mode.

2. The computer system of claim 1, the computer system further comprising:

a latch device arranged to latch the data signal.

3. The computer system of claim 2, the computer system further comprising:

an adjustment circuit arranged to adjust a timing of an adjustable clock signal dependent on the clock signal and the calibration circuitry, wherein the latch device is responsive to the adjustable clock signal.

4. The computer system of claim 3, wherein the adjustable clock signal is generated from one selected from the group consisting of a voltage controlled delay line, a digital delay line, and an analog delay line.

5. The computer system of claim 2, the computer system further comprising:

a pattern comparator arranged to generate an output signal dependent on a comparison of a latched test pattern signal and a test pattern signal, wherein the latch device is arranged to latch the test pattern signal from the data signal to generate the latched test pattern signal.

6. The computer system of claim 5, wherein the calibration circuitry is arranged to receive the output signal from the pattern comparator.

7. The computer system of claim 1, wherein the calibration circuitry is dependent on a counter.

8. The computer system of claim 1, further comprising:

circuitry arranged to generate the power mode control signal.

9. The computer system of claim 8, wherein the circuitry is arranged to initiate a test of the transmission link.

10. The computer system of claim 1, wherein the calibration circuitry is arranged to initiate a test of the transmission link.

11. A method for updating data communication, comprising:

transmitting a clock signal and a data signal; and

latching the data signal dependent on an adjustable clock signal, wherein the adjustable clock signal is dependent on the clock signal;

when in a low power mode,

transmitting a test pattern signal on the data signal,

latching the test pattern signal to generate a latched test pattern signal,

comparing the test pattern signal and the latched test pattern signal, and

adjusting the adjustable clock signal dependent on the comparing.

12. The method of claim 11, the adjusting comprising:

delaying the clock signal.

13. A computer system having at least a portion capable of operating in a low power mode and a normal mode, comprising:

means for propagating a data signal and a clock signal;

means for latching the data signal dependent on an adjustable clock signal, wherein the adjustable clock signal dependent on the clock signal; and

means for adjusting the adjustable clock signal when in the low power mode.

14. The computer system of claim 13, the means for adjusting comprising:

means for comparing a latched test pattern signal and a test pattern signal; and

means for delaying the clock signal to generate the adjustable clock signal dependent on the means for comparing.

15. A computer system, comprising:

a transmission link arranged to propagate a data signal and a clock signal; and

calibration circuitry operatively connected to the clock signal and capable of updating a receipt time of the data signal when the transmission link is in at least one of a low activity state and a low power mode.

16. The computer system of claim 15, wherein the low activity state occurs when a particular amount of data has not been transferred across the transmission link in a particular amount of time.

17. The computer system of claim 15, the computer system further comprising:

an adjustment circuit arranged to adjust a timing of an adjustable clock signal dependent on the clock signal and the calibration circuitry, wherein a latch device arranged to latch the data signal is responsive to the adjustable clock signal.

18. The computer system of claim 17, wherein the adjustable clock signal is generated from one selected from the group consisting of a voltage controlled delay line, a digital delay line, and an analog delay line.

19. The computer system of claim 17, the computer system further comprising:

a pattern comparator arranged to generate an output signal dependent on a comparison of a latched test pattern signal and a test pattern signal, wherein the latch device is arranged to latch the test pattern signal from the data signal to generate the latched test pattern signal.

20. The computer system of claim 19, wherein the calibration circuitry is arranged to receive the output signal from the pattern comparator.