Method and apparatus for image processing

• US 20040156546A1
• Filed: 01/15/2004
• Published: 08/12/2004
• Est. Priority Date: 01/17/2003
• Status: Active Grant

• Current Assignee: Parimics Incorporated
• Original Assignee: Parimics Incorporated
• Inventors: Kloth, Axel K.
• Granted Patent: US 7,489,834 B2
• Time in Patent Office: Days
• US Class Current: 382/181
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06V 10/94 Hardware or software architectures specially adapted for image or video understanding

Abstract

An image processing system processes images via a first processing layer adapted to perform object-independent processing, a second processing layer adapted to perform object-dependent processing, and a third processing layer adapted to perform object composition, recognition and association. The image processing system performs object-independent processing using a plurality of processors each of which is associated with a different one of the pixels of the image. The image processing system performs object-independent processing using a symmetric multi-processor. The plurality of processors may form a massively parallel processor of a systolic array type and configured as a single-instruction multiple-data system. Each of the plurality of the processors is further configured to perform object-independent processing using a unified and symmetric processing of N dimensions in space and one dimension in time. The plurality of processors are formed on a semiconductor substrate different from the semiconductor substrate on which images are captured.

Claims

1. An image processing system comprising:

a first processing layer adapted to perform object-independent processing, wherein said object-independent processing is further adapted to include a plurality of processors corresponding to the first processing layer, and wherein each of the plurality of the processors is associated with a different one of pixels of an image frame;

a second processing layer adapted to perform object-dependent processing; and

a third processing layer adapted to perform object recognition and association.

2. The image processing system of claim 1 wherein said object-dependent processing is further adapted to be performed by a symmetric multi-processor.

3. The image processing system of claim 1 wherein the plurality of processors adapted to perform object independent processing form a massively parallel processing system.

4. The image processing system of claim 3 wherein the massively parallel processing system is a systolic array type massively parallel processing system.

5. The image processing system of claim 4 wherein the systolic array type massively parallel processing system is configured as a single-instruction multiple-data system.

6. The image processing system of claim 1 wherein each of the plurality of the processors adapted to perform object independent processing is enabled to perform a unified and symmetric processing of N dimensions in space and one dimension in time.

7. The image processing system of claim 1 further comprising:

an image capturing block.

8. The image processing system of claim 7 wherein the plurality of processors are formed on a first semiconductor substrate different from a second semiconductor substrate on which the image capturing block is formed.

9. The image processing system of claim 8 further comprising:

a realignment buffer adapted to realign the data received from first and second analog-to-digital converters disposed in the image capturing block.

10. A method for processing images:

performing object-independent processing in a first processing layer;

performing object-dependent processing in a second processing layer; and

performing object recognition and association in a third processing layer.

11. The method of claim 10 further comprising:

performing object-independent processing by a plurality of processors each associated with a different one of pixels of an image frame being processed.

12. The method of claim 11 further comprising:

performing object-dependent processing by a symmetric multi-processor.

13. The method of claim 11 further comprising:

performing object independent processing by a plurality of processors that form a massively parallel processing system.

14. The method of claim 13 wherein the massively parallel processing system is a systolic array type massively parallel processing system.

15. The method of claim 14 further comprising:

configuring the systolic array massively parallel processing system as a single-instruction multiple-data system.

16. The method of claim 11 wherein each of the plurality of the processors is enabled to perform a unified and symmetric processing of N dimensions in space and one dimension in time.

17. The method of claim 11 further comprising:

capturing the image frame on a first semiconductor substrate that is different from a second semiconductor substrate on which the plurality of processors are formed.

18. The method of claim 17 further comprising converting analog data corresponding to the image frame to digital data;

and

realigning the converted digital data.