Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step

• US 20040157384A1
• Filed: 02/02/2004
• Published: 08/12/2004
• Est. Priority Date: 03/21/2002
• Status: Active Grant

• Current Assignee: Richard A. Blanchard
• Original Assignee: Richard A. Blanchard
• Inventors: Blanchard, Richard A.
• Granted Patent: US 7,084,455 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and forming a voltage sustaining region on the substrate. The voltage sustaining region is formed in the following manner. First, an epitaxial layer is deposited on the substrate. The epitaxial layer has a first or a second conductivity type. Next, at least one terraced trench is formed in the epitaxial layer. The terraced trench has a trench bottom and a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls and bottom of the trench. A dopant of a conductivity type opposite to the conductivity type of the epitaxial layer is implanted through the barrier material lining the annular ledge and at the trench bottom and into adjacent portions of the epitaxial layer to respectively form at least one annular doped region and another doped region. The dopant is diffused in the annular doped region and the another doped region to cause the regions to overlap one another, whereby a continuous doped column is formed in the epitaxial layer. A filler material is deposited in the terraced trench to substantially fill the terraced trench. Finally, at least one region of conductivity type opposite to the conductivity type of the epitaxial layer is formed over the voltage sustaining region to define a junction therebetween.

Claims

1. A method of forming a power semiconductor device comprising the steps of:

A. providing a substrate of a first conductivity type;

B. forming a voltage sustaining region on said substrate by;

1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first or a second conductivity type;

2. forming at least one terraced trench in said epitaxial layer, said terraced trench having a trench bottom and a plurality of portions that differ in width to define at least one annular ledge therebetween;

3. depositing a barrier material along the walls and bottom of said trench;

4. implanting a dopant of a conductivity type opposite to the conductivity type of the epitaxial layer through the barrier material lining at said at least one annular ledge and at said trench bottom and into adjacent portions of the epitaxial layer to respectively form at least one annular doped region and another doped region;

5. diffusing the dopant in said at least one annular doped region and said another doped region to cause said at least one annular doped region and said another doped region to overlap one another, whereby a continuous doped column is formed in said epitaxial layer;

6. depositing a filler material in said terraced trench to substantially fill said terraced trench; and

C. forming over said voltage sustaining region at least one region of conductivity type opposite to the conductivity type of the epitaxial layer to define a junction therebetween.

2. The method of claim 1 wherein the step of forming said at least one terraced trench includes the steps of successively etching the plurality of portions of the terraced trench beginning with a largest width portion and ending with a smallest width portion.

3. The method of claim 2 wherein said smallest width portion is located at a depth in said epitaxial layer such that it is closer to the substrate than the largest width portion.

4. The method of claim 1 wherein said plurality of portions of the terraced trench are coaxially located with respect to one another.

5. The method of claim 1 wherein said plurality of portions of the terraced trench includes at least three portions that differ in width from one another to define at least two annular ledges and said at least one annular doped region includes at least two annular doped regions.

6. The method of claim 4 wherein said plurality of portions of the terraced trench includes at least three portions that differ in width from one another to define at least two annular ledges and said at least one annular doped region includes at least two annular doped regions.

7. The method of claim 6 wherein the step of forming at least one terraced trench includes the steps of successively etching said at least three portions of the terraced trench beginning with a largest width portion and ending with a smallest width portion.

8. The method of claim 7 wherein said smallest width portion is located at a depth in said epitaxial layer such that it is closer to the substrate than said largest width portion.

9. The method of claim 1 wherein step (C) further includes the steps of:

forming a gate conductor above a gate dielectric region;

forming first and second body regions in the epitaxial layer to define a drift region therebetween, said body regions having a conductivity type opposite to the conductivity type of the epitaxial layer;

forming first and second source regions of the first conductivity type in the first and second body regions, respectively.

10. The method of claim 1 wherein said barrier material is an oxide material.

11. The method of claim 10 wherein said oxide material is silicon dioxide.

12. The method of claim 1 wherein said epitaxial layer has a given thickness and further comprising the step of etching a first portion of the terraced trench by an amount substantially equal to 1/(x+1) of said given thickness, where x is equal to or greater than a prescribed number of annular doped regions to be formed in the voltage sustaining region, said prescribed number of annular doped regions collectively defining said continuous doped column.

13. The method of claim 1 wherein said material filling the trench is a dielectric material.

14. The method of claim 13 wherein said dielectric material is silicon dioxide.

15. The method of claim 13 wherein said dielectric material is silicon nitride.

16. The method of claim 1 wherein said dopant is boron.

17. The method of claim 9 wherein said body regions include deep body regions.

18. The method of claim 1, wherein said terraced trench is formed by providing a masking layer defining at least a first of said plurality of portions and etching said first portion defined by the masking layer

19. The method of claim 18 further comprising the step of depositing an oxide layer of prescribed thickness along the walls of said first portion of the terraced trench.

20. The method of claim 19 wherein said oxide layer serves as a second masking layer and further comprising the step of etching a second portion of the terraced trench defined by the second masking layer through a bottom surface of the first portion of the terraced trench.

21. The method of claim 20 wherein said prescribed thickness of the oxide layer is selected so that a surface area of said at least one annular ledge and the trench bottom region are substantially equal to one another.

22. The method of claim 9, wherein said body region is formed by implanting and diffusing a dopant into the substrate.

23. The method of claim 1 wherein said power semiconductor device is selected from the group consisting of a vertical DMOS, V-groove DMOS, and a trench DMOS MOSFET, an IGBT, and a bipolar transistor.

24. The method of claim 1 wherein each ledge has an area substantially equal to an area of the trench bottom and wherein a distance between adjacent ledges is substantially equal to a distance between the trench bottom and a bottommost one of the ledges.

25. The method of claim 1 wherein an area of each ledge divided by an average distance between adjacent edges are substantially equal.

27. A power semiconductor device made in accordance with the method of claim 1.

28. A power semiconductor device made in accordance with the method of claim 7.

29. A power semiconductor device made in accordance with the method of claim 9.

26.

30. A power semiconductor device comprising:

a substrate of a first conductivity type;

a voltage sustaining region disposed on said substrate, said voltage sustaining region including;

an epitaxial layer having a first or second conductivity type;

at least one terraced trench located in said epitaxial layer, said terraced trench having a trench bottom and a plurality of portions that differ in width to define at least one annular ledge therebetween;

at least one doped column having a dopant of a conductivity type opposite to the conductivity type of the epitaxial layer, said doped column being formed from at least one annular doped region and another doped region diffused into one another, said at least one annular region and said another doped region being located in said epitaxial layer adjacent to and below said at least one annular ledge and said trench bottom, respectively;

a filler material substantially filling said terraced trench; and

at least one active region of a conductivity opposite to the conductivity type of the epitaxial layer disposed over said voltage sustaining region to define a junction therebetween.

31. The device of claim 30 wherein said plurality of portions of the terraced trench includes a smallest width portion and a largest width portion, said smallest width portion being located at a depth in said epitaxial layer such that it is closer to the substrate than a largest width portion.

32. The device of claim 31 wherein said plurality of portions of the terraced trench are coaxially located with respect to one another.

33. The device of claim 30 wherein said plurality of portions of the terraced trench includes at least three portions that differ in width from one another to define at least two annular ledges and said at least one annular doped region includes at least two annular doped regions.

34. The device of claim 32 wherein said plurality of portions of the terraced trench includes at least three portions that differ in width from one another to define at least two annular ledges and said at least one annular doped region includes at least two annular doped regions.

35. The device of claim 30 wherein said epitaxial layer has a given thickness and further comprising the step of etching a first portion of the terraced trench by an amount substantially equal to 1/(x+1) of said given thickness, where x is equal to or greater than a prescribed number of annular doped regions to be formed in the voltage sustaining region.

36. The device of claim 30 wherein said material filling the trench is a dielectric material.

37. The device of claim 36 wherein said dielectric material is silicon dioxide.

38. The device of claim 37 wherein said dielectric material is silicon nitride.

39. The device of claim 30 wherein said dopant is boron.

40. The device of claim 34 wherein a surface area of the at least two annular ledges are substantially equal to one another.

41. The device of claim 30 wherein said at least one active region further includes:

a gate dielectric and a gate conductor disposed above said gate dielectric;

first and second body regions located in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type; and

first and second source regions of the first conductivity type located in the first and second body regions, respectively.

42. The device of claim 41 wherein said body regions include deep body regions.

43. The device of claim 30 wherein said terraced trench has a circular cross-section.

44. The device of claim 30 wherein said terraced trench has a cross-sectional shape selected from the group consisting of a square, rectangle, octagon, and a hexagon.