Transfer of a thin layer from a wafer comprising a buffer layer

• US 20040157409A1
• Filed: 07/08/2003
• Published: 08/12/2004
• Est. Priority Date: 07/09/2002
• Status: Active Grant

• Current Assignee: Soitec Silicon On Insulator Technologies SA (Soitec S.A.)
• Original Assignee: Soitec Silicon On Insulator Technologies SA (Soitec S.A.)
• Inventors: Ghyselen, Bruno, Aulnette, Cecile, Osternaud, Benedite
• Granted Patent: US 7,018,910 B2
• Time in Patent Office: Days
• US Class Current: 438/458
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76259 with separation/delamination along a porous layer
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

A process for producing a structure of a thin layer of semiconductor material obtained from a composite structure donor wafer. The donor wafer includes a lattice parameter matching layer of a matching substrate that advantageously has an upper layer of semiconductor material having a first lattice parameter. A film of semiconductor material having a second, nominal, lattice parameter that is substantially different from the first lattice parameter is strained by the matching layer. A region of weakness is created in the matching substrate to facilitate splitting. A relaxed layer has a nominal lattice parameter that is substantially identical to the first lattice parameter. The relaxed layer is transferred to a receiving substrate. A number of different wafers can be made by this process.

Claims

1. A method of preparing a semiconductor wafer, comprising:

growing a first layer of a first material on a matching substrate comprising a matching layer;

growing a second layer of a semiconductor second material, different from the first material, in a relaxed state on the first layer to form a boundary between the first and second layers and to form a composite structure which comprises the matching, first, and second layers, wherein the first and second layers each have substantially the same first lattice parameter;

creating a region of weakness in the matching substrate to facilitate splitting; and

removing the first layer from the second layer to produce a boundary on the second layer that is substantially smooth and of substantially uniform thickness.

2. The method of claim 1, where the first layer is grown in a strained state.

3. The method of claim 1, wherein the matching layer has the lattice parameter where it contacts the first layer that is substantially the same as the first lattice parameter of the first layer.

4. The method of claim 1, further comprising growing the matching layer on a handling substrate that has a second lattice parameter that is different from the first lattice parameter.

5. The method of claim 1, wherein the matching layer includes a buffer layer and a relaxed surface layer.

6. The method of claim 5, wherein the lattice parameter of the matching layer is graded between the first and second lattice parameters.

7. The method of claim 6, wherein the region of weakness is created in a portion of the matching layer that is in a substantially relaxed state.

8. The method of claim 1, further comprising splitting the composite structure into:

an unfinished wafer that includes the second layer, and

a handle wafer that includes a portion of the matching layer.

9. The method of claim 8, wherein the composite structure is split such that the unfinished wafer includes the first layer.

10. The method of claim 8, further comprising associating a receiving substrate with the second layer of the composite structure prior to splitting.

11. The method of claim 10, wherein the receiving substrate is bonded to the second layer.

12. The method of claim 1, further comprising providing an insulator between the second layer and receiving substrate.

13. The method of claim 1, wherein the region of weakness is created by implanting atomic species.

14. The method of claim 1, wherein the region of weakness is created by adding a porous layer.

15. The method of claim 1, wherein the first layer is strained to impart the first lattice parameter.

16. The method of claim 15, wherein the lattice parameter of the first material when strained is different than the lattice parameter of the first material in a relaxed state.

17. The method of claim 1, further comprising:

splitting the composite structure into;

an unfinished wafer that includes the second layer and at least a remaining portion of the matching layer, and

a handle wafer; and

removing the remaining portion of the matching layer from the unfinished wafer.

18. The method of claim 17, wherein the first layer is removed by etching.

19. The method of claim 17, further comprising thickening the remaining portion of the first layer.

20. The method of claim 1, wherein the boundary with the first layer removed is sufficiently smooth for growing a substantially uniform and substantially smooth device layer thereon of a semiconductor material that is different from that of the second layer and that has a lattice parameter that is adapted to match that of the second layer.

21. The method of claim 1, wherein the first material is a semiconductor.

22. The method of claim 1, further comprising growing a device layer on the boundary.

23. The method of claim 1, wherein the region of weakness is created at a depth from the second layer sufficient for substantially preventing damage to the second layer.

24. The method of claim 23, wherein a damaged region in the matching substrate and outside the second layer is created adjacent the region of weakness by the creation of the region of weakness.

25. The method of claim 1, wherein the matching layer and the second layer comprise silicon germanium.

26. A semiconductor wafer, comprising:

a matching substrate that includes a matching layer having at least a first lattice parameter, the matching substrate having a region of weakness configured to facilitate splitting;

a first layer of a first material grown directly on the matching layer and having a lattice parameter that is substantially that same as the first lattice parameter; and

a second layer grown on the first layer and comprising a semiconductor second material in a relaxed state that is different from the first material and that has a lattice parameter that is substantially the same as the first lattice parameter.

27. The wafer of claim 26, further comprising a handling substrate on which the matching layer is grown and configured for supporting the matching, first, and second layers.

28. The wafer of claim 26, further comprising a receiving substrate supportively associated with the second layer.

29. The wafer of claim 26, wherein the first layer is stressed to impart the first lattice parameter.

30. The wafer of claim 26, further comprising an insulator disposed between the second layer and receiving substrate.

31. The wafer of claim 26, wherein the matching layer includes a buffer layer and a relaxed surface layer.

32. The wafer of claim 31, wherein the buffer layer is graded between the first and second lattice parameters.

33. The wafer of claim 26, wherein the matching substrate comprises a damaged region that only extends substantially outside the second layer and is disposed adjacent the region of weakness.

34. A method of preparing a semiconductor wafer, comprising:

growing a first layer of a first material on a matching substrate comprising a matching layer;

growing a second layer of a semiconductor second material, different from the first material, in a relaxed state on the first layer to form a boundary between the first and second layers and to form a composite structure which comprises the matching, first, and second layers, wherein the first and second layers each have substantially the same first lattice parameter;

creating a region of weakness in the matching substrate to facilitate splitting;

splitting the composite structure into;

an unfinished wafer that includes the second layer and at least a remaining portion of the first layer, and

a handle wafer that includes a portion of the matching layer;

thickening the remaining portion of the first layer.

35. The method of claim 34, wherein the composite structure is split such that the unfinished wafer includes the a remaining portion of the matching layer, the method further comprising removing the remaining portion of the matching layer prior to the thickening of the remaining portion of the first layer.