Fabrication of advanced silicon-based MEMS devices

• US 20040157426A1
• Filed: 04/10/2003
• Published: 08/12/2004
• Est. Priority Date: 02/07/2003
• Status: Abandoned Application

• Current Assignee: Dalsa Semiconductor Inc (Teledyne Technologies Incorporated)
• Original Assignee: Dalsa Semiconductor Inc (Teledyne Technologies Incorporated)
• Inventors: Ouellet, Luc, Antaki, Robert
• Application Number:
  US10/410,158
• Publication Number:
  US 20040157426A1
• Time in Patent Office: Days
• US Class Current: 438/618
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/00666 Treatments for controlling internal stress or strain in MEMS structures
• CPC Class Codes: B81C 2201/0164 by doping the layer
• CPC Class Codes: B81C 2201/0167 by adding further layers of materials having complementary strains, i.e. compressive or tensile strain
• CPC Class Codes: B81C 2201/0169 by post-annealing
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit

Abstract

A micro-electro-mechanical (MEM) device and an electronic device are fabricated on a common substrate by fabricating the electronic device comprising a plurality of electronic components on the common substrate, depositing a thermally stable interconnect layer on the electronic device, encapsulating the interconnected electronic device with a protective layer, forming a sacrificial layer over the protective layer, opening holes in the sacrificial layer and the protective layer to allow the connection of the MEM device to the electronic device, fabricating the MEM device by depositing and patterning at least one layer of amorphous silicon, and removing at least a portion of the sacrificial layer. In this way, the MEM device can be fabricated after the electronic device on the same substrate.

Claims

1. A method fabricating a micro-electro-mechanical (MEM) device and an electronic device on a common substrate comprising the steps of:

fabricating said electronic device comprising a plurality of electronic components on said common substrate;

depositing a thermally stable interconnect layer on said electronic device;

encapsulating the interconnected electronic device with a protective layer;

forming a sacrificial layer over said protective layer;

opening holes in the sacrificial layer and said protective layer to allow the connection of the MEM device to said electronic device;

fabricating said MEM device by depositing and patterning at least one layer of amorphous silicon; and

removing at least a portion of said sacrificial layer.

2. The method of claim 1, wherein said interconnect layer includes a contact material incorporating a refractory material ensuring thermally stable contact resistance to N+ doped silicon, P+ doped silicon, and polysilicon.

3. The method of claim 2, wherein said contact material is selected from the group consisting of titanium Ti;

titanium-tungsten allow, TiW;

titanium nitride, TiN;

titanium silicide, TiSi₂;

a combinations thereof.

4. The method of claim 1, wherein the interconnect layer comprises a material selected from the group consisting of:

aluminum;

an aluminum-silicon binary alloy plug containing less then 2.0 wt % of silicon, as to ensure a silicon-eutectic temperature of more then 567°

C.;

an aluminum-copper binary alloy plug containing less than 6.0 wt % of copper to ensure a silicon-eutectic temperature of more than 548°

C.;

another binary aluminum alloy plug having an eutectic temperature higher than 545°

C.;

an aluminum-silicon-copper ternary alloy containing less than 2.0 wt % of silicon and less than 6.0 wt % of copper;

a ternary aluminum alloy having an eutectic temperature higher than 545°

C., Copper;

Tungsten;

a combination thereof.

5. The method of claim 1, wherein the interconnect layer comprises a layered structure ensuring thermally stable interconnects, said layered interconnection structure comprising a titanium-based under-layer, an aluminum-based middle-layer, and a titanium-based over-layer.

7. The method of claim 1, wherein said interconnect layer has a layered structure comprising a tantalum-based under-layer;

a copper-based middle layer;

a tantalum-based over-layer.

8. The method of claim 1, wherein the interconnect layer comprises a layered interconnection structure comprising a titanium-based under-layer and a tungsten-based layer.

9. The method of claim 8, wherein said titanium-based under-layer is selected from the group consisting of:

titanium, Ti, titanium nitride, TiN or combinations of Ti and TiN;

and said tungsten-based layer is CVD-W.

10. The method of claim 1, wherein the interconnect layer is a layered interconnection structure comprising a titanium-based under-layer;

a tungsten-based middle-layer, such as CVD-W;

a titanium-based over-layer, such as titanium, Ti, titanium nitride, TiN or combinations of Ti and TiN.

11. The method as claimed in claim 10, wherein said titanium-based under-layer is selected from the group consisting of titanium, Ti, titanium nitride, TiN or combinations thereof;

said tungsten-based middle-layer is CVD-W; and

said titanium-based over-layer is selected from the group consisting of;

titanium, Ti, titanium nitride, TiN or combinations of Ti and TiN.

12. The method of claim 1 wherein said protective layer comprises a layer selected from the group consisting of:

an un-doped amorphous silicon layer a-Si;

a phosphorus-doped amorphous silicon layer a-Si(P);

a titanium, Ti, layer;

a titanium nitride, TiN, layer;

an aluminum alloy layer;

a plasma-enhanced chemical vapor deposited, PECVD, silicon nitride layer;

a spin-on polymer layer;

or a combination thereof.

13. The method of claim 1, wherein said sacrificial layer is selected from the group consisting of:

a silicate glass, SG, layer;

a phosphorus-doped silicate glass, PSG, layer;

a boron-doped silicate glass, BSG, layer;

a boron- and phosphorus-doped silicate glass, BPSG, layer;

a tetraethyl-ortho-silicate-glass, TEOS, layer;

a fluorinated dielectric;

a highly porous dielectric;

a silicate spin-on glass, SOG, layer;

a phosphorus-doped silicate SOG layer or;

combinations thereof.

14. The method of claim 1, wherein the opening of the holes in the sacrificial layer and in the protective layer permit the establishment of connections to a circuit element selected from the group consisting of:

an N+ junction;

a P+ junction;

a polysilicon layer;

an interconnection;

or combinations thereof.

15. The method of claim 1, wherein said at least one amorphous silicon layer is deposited at a temperature of less than 580°

C.

16. The method of claim 1, wherein said at least one amorphous silicon layer is deposited at a temperature between 520 and 550°

C.

17. The method of claim 1, wherein said at least one layer of amorphous silicon is deposited using silane partial pressure of less than 5000 mTorr.

18. The method of claim 1, wherein said at least one layer of amorphous silicon is deposited using silane partial pressure of between 100 and 500 mTorr.

19. The method of claim 1, wherein said at least one layer of amorphous silicon is phosphorus-doped using a phosphine partial pressure of less than 5 mTorr.

20. The method of claim 1, wherein said at least one layer of amorphous silicon is phosphorus-doped using a phosphine partial pressure of between 0.10 and 0.50 mTorr;

21. The method of claim 1, wherein said at least one layer of amorphous silicon is phosphorus-doped as to provide a bulk resistivity of less than 1000 mohm.cm.

22. The method of claim 1, wherein said at least one layer of amorphous silicon is phosphorus-doped as to provide a bulk resistivity of between 0.1 and 1 mohm.cm. less than 1000 mohm.cm.

23. The method of claim 1, wherein said at least one layer of amorphous silicon is un-doped and has a compressive mechanical stress of less than −

400 MPa.

24. The method of claim 1, wherein said at least one layer of amorphous silicon is un-doped and has a compressive mechanical stress of between −

0.01 MPa and −

10 MPa.

25. The method of claim 1, wherein the at least one layer of amorphous silicon is phosphorus-doped and has a tensile mechanical stress of less than +400 MPa.

26. The method of claim 1, wherein the at least one layer of amorphous silicon is phosphorus-doped and has a tensile mechanical stress of between +0.01 MPa and +10 MPa.

27. The method of claim 1, wherein the at least one layer of amorphous silicon is slightly phosphorus-doped and has a low residual mechanical stress of less than −

100 MPa.

28. The method of claim 1, wherein the at least one layer of amorphous silicon is slightly phosphorus-doped and has a low residual mechanical stress of less than −

100 MPa.

29. The method of claim 1, wherein comprising several said layers of amorphous silicon forming a laminated structure combining un-doped and phosphorus-doped layers, said laminated structure to having a low residual mechanical stress of less than −

100 MPa.

30. The method of claim 1, wherein the at least one layer of amorphous silicon is un-doped and has an absolute stress gradient of less than 20 MPa/μ

m.

31. The method of claim 1, wherein the at least one layer of amorphous silicon is phosphorus-doped and has an absolute stress gradient of less than 20 MPa/μ

m.

32. The method of claim 1, wherein the at least one layer of amorphous silicon is slightly phosphorus-doped and has a low absolute stress gradient of less than 5 MPa/μ

m.

33. The method of claim 1, comprising several layers of amorphous silicon forming a laminated structure combining un-doped and phosphorus-doped layers, said laminated having a low absolute stress gradient of\less than 5 MPa/μ

m.

6. The method of claim 6, wherein said titanium-based under-layer is selected from the group consisting of:

titanium, Ti, titanium nitride, TiN or combinations of Ti and TiN;

said an aluminum-based middle-layer is selected from the group consisting of;

aluminum, Al;

an aluminum-silicon binary alloy containing less then 2.0 wt % of silicon, as to ensure a silicon-eutectic temperature of more than 567°

C.;

an aluminum-copper binary alloy containing less than 6.0 wt % of copper, as to ensure a silicon-eutectic temperature of more than 548°

C.;

a binary aluminum alloy having an eutectic temperature higher than 545°

C.;

an aluminum-silicon-copper ternary alloy containing less than 2.0 wt % of silicon and less than 6.0 wt % of copper;

a ternary aluminum alloy having an eutectic temperature higher than 545°

C.; and

said titanium based over-layer is selected from the group consisting of;

titanium, Ti, titanium nitride, TiN or combinations of Ti and TiN.