Photoresist intensive patterning and processing

• US 20040157444A1
• Filed: 02/10/2003
• Published: 08/12/2004
• Est. Priority Date: 02/10/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tao, Hun-Jan, Chiu, Yuan-Hung, Tsai, Ming-Huan, Chen, Jeng-Horng
• Granted Patent: US 7,078,351 B2
• Time in Patent Office: Days
• US Class Current: 438/689
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02263 deposition from the gas or vapour phase
• CPC Class Codes: H01L 21/0276 using an anti-reflective coating anti-reflective coating for lithography in general G03F7/09
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/3145 formed by deposition from a gas or vapour
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics

Abstract

A layer of Anti Reflective Coating (ARC) is first deposited over the surface of a silicon based or oxide based semiconductor surface, a dual hardmask is deposited over the surface of the layer of ARC. A layer of soft mask material is next coated over the surface of the dual hardmask layer, the layer of soft mask material is exposed, creating a soft mask material mask. The upper layer of the dual hardmask layer is next patterned in accordance with the soft mask material mask, the soft mask material mask is removed from the surface. The lower layer of the hardmask layer is then patterned after which the layer of ARC is patterned, both layers are patterned in accordance with the patterned upper layer of the dual hardmask layer. The substrate is now patterned in accordance with the patterned upper and lower layer of the dual hardmask layer and the patterned layer of ARC. The patterned upper and lower layers of the hardmask layer and the patterned layer of ARC are removed from the surface of the silicon based or oxide based semiconductor surface.

Claims

9. A method for patterning a semiconductor surface by applying etch processes, comprising:

forming a layer on a substrate;

forming a first hardmask with a first thickness on said layer;

forming a second hardmask with a second thickness on said first hard mask;

forming a third mask with a third thickness over said second hard mask, the third thickness of the third hard mask being thinner than the second thickness of the second hard mask, the third hard mask comprising material different than material of the second hardmask, assuring an etch selectivity between the third and the second hard mask;

forming a soft mask over the third hard mask;

patterning and etching the soft mask, exposing the surface of the third hard mask;

etching the exposed surface of the third hard mask, exposing the surface of the second hard mask;

etching the exposed surface of the second hard mask, exposing the surface of the first hard mask;

etching the exposed surface of the first hard mask, exposing the layer on the substrate; and

etching the exposed surface of the layer on the substrate.

10. The method of claim 9, said second hardmask comprising a material selected from the group consisting of silicon dioxide and silicon nitride and silicon oxynitride and combinations thereof.

11. The method of claim 10, said second thickness of said second hard mask being in the range between about 500 and 9,000 Angstrom.

12. The method of claim 10, said third layer of hardmask comprising a material selected from the group consisting of silicon dioxide and silicon nitride and silicon oxynitride and combinations thereof.

13. The method of claim 10, said third thickness of said third hard mask being in the range between 300 and 6,000 Angstrom.

14. The method of claim 10, said first hardmask also serving as a BARC.

15. The method of claim 14, said layer of BARC being formed by CVD.

16. The method of claim 16, said layer of BARC comprising amorphous carbon.

17. A method for patterning a semiconductor surface by applying etch processes, comprising:

forming a layer on a substrate;

forming a layer of BARC over the surface of said layer on the substrate;

forming a first hardmask with a first thickness on the layer of BARC;

forming a second hardmask with a second thickness on said first hardmask, the second thickness of the second hard mask being thinner than the first thickness of the first mask, the second hard mask comprising material different than material of the first hardmask, assuring an etch selectivity between the first and the second hard mask;

forming a soft mask over said second hard mask;

patterning and etching the soft mask, exposing the surface of the second hard mask;

etching the exposed surface of the second hard mask, exposing the surface of the first hard mask;

etching the exposed surface of the first hard mask, exposing the layer on the substrate; and

etching the exposed surface of the layer on the substrate.

1. A method for patterning a semiconductor surface by applying etch processes, comprising:

forming a layer on a substrate;

forming a first hardmask with a first thickness on said layer;

forming a second hardmask with a second thickness on said first hard mask, the second thickness of the second hard mask being less than the first thickness of the first mask, the second hard mask comprising material different than material of the first hardmask, assuring an etch selectivity between the first and the second hard mask;

forming a soft mask over said second hard mask;

patterning and etching the soft mask, exposing the surface of the second hard mask;

etching the exposed surface of the second hard mask, exposing the surface of the first hard mask;

etching the exposed surface of the first hard mask, exposing the layer on the substrate; and

etching the exposed surface of the layer on the substrate.

2. The method of claim 1, said first hardmask comprising a material selected from the group consisting of silicon dioxide and silicon nitride and silicon oxynitride and combinations thereof.

3. The method of claim 1, said first thickness of said first hard mask being in the range between about 500 and 9,000 Angstrom.

4. The method of claim 1, said second layer of hardmask comprising a material selected from the group consisting of silicon dioxide and silicon nitride and silicon oxynitride and combinations thereof.

5. The method of claim 1, said second thickness of said second hard mask being in the range between 300 and 6,000 Angstrom.

6. The method of claim 1, further comprising a step of forming a layer of BARC over the surface of said layer on the substrate.

7. The method of claim 6, said layer of BARC being formed by CVD.

8. The method of claim 7, said layer of BARC comprising amorphous carbon.

18. The method of claim 17, said first hardmask comprising a material selected from the group consisting of silicon dioxide and silicon nitride and silicon oxynitride and combinations thereof.

19. The method of claim 17, said first thickness of said first hard mask being in the range between about 500 and 9,000 Angstrom.

20. The method of claim 17, said second layer of hardmask comprising a material selected from the group consisting of silicon dioxide and silicon nitride and silicon oxynitride and combinations thereof.

21. The method of claim 17, said second thickness of said second hard mask being in the range between 300 and 6,000 Angstrom.

22. The method of claim 17, said layer of BARC being formed by CVD.

22-1. The method of claim 17, said layer of BARC comprising amorphous carbon.

23. A method for patterning a semiconductor surface by applying etch processes, comprising:

forming a layer on a substrate;

forming a first hardmask comprising amorphous carbon with a first thickness on said layer, said first hardmask functioning as a BARC;

forming a second hardmask with a second thickness on said first hard mask;

forming a third mask with a third thickness over said second hard mask, the third thickness of the third hard mask being thinner than the second thickness of the second hard mask, the second hard mask comprising material different than material of the first hardmask, assuring an etch selectivity between the first and the second hard mask;

forming a soft mask over the third hard mask;

patterning and etching the soft mask, exposing the surface of the third hard mask;

etching the exposed surface of the third hard mask, exposing the surface of the second hard mask;

etching the exposed surface of the second hard mask, exposing the surface of the first hard mask;

etching the exposed surface of the first hard mask, exposing the layer on the substrate; and

etching the exposed surface of the layer on the substrate.

24. The method of claim 23, said second hardmask comprising a material selected from the group consisting of silicon dioxide and silicon nitride and silicon oxynitride and combinations thereof.

25. The method of claim 23, said second thickness of said first hard mask being in the range between about 500 and 9,000 Angstrom.

26. The method of claim 23, said third layer of hardmask comprising a material selected from the group consisting of silicon dioxide and silicon nitride and silicon oxynitride and combinations thereof.

27. The method of claim 23, said third thickness of said second hard mask being in the range between 300 and 6,000 Angstrom.

28. The method of claim 23, said first hardmask layer being formed by CVD.